1. Andrei Nomerotski 1 Andrei Nomerotski, University of Oxford Ringberg Workshop, 8 April 2008 Pixels with Internal Storage: ISIS by LCFI

2. Andrei Nomerotski 2 Outline  Principle of operation  ISIS1  ISIS2 design and status  ISIS with 3D vertical integration

3. Andrei Nomerotski 3 Readout for ILC  Massive e + e - background from beamstrahlung : pairs radiated in intense EM fields of bunches  Need to read out pixels in vertex detector once occupancy = 1% u 20 times per train  Main idea: Each pixel has a 20-cell storage u Charge is stored INSIDE the pixel during collisions and read out during quiet time 337 ns 2820x 0.2 s 0.95 ms LC Beam Time Structure : = one train

4. Andrei Nomerotski 4 ISIS – In-Situ Storage Image Sensor  Each pixel has internal memory implemented as CCD register u Charge collected under a photogate u Charge is transferred to 20-pixel storage CCD in situ u Conversion to voltage and readout in the 200 ms-long quiet period after collisions  Visible light imagers based on the ISIS principle are available off- the-shelf (ex. DALSA, 100 MHz camera with 16 storage cells) Ch.Damerell

5. Andrei Nomerotski 5 ISIS by LCFI  Advantages u Store raw charge – robust to EMI issues u Slow readout after collisions u Small number of transfers – radiation hard  Difficulty u Non-standard process – need features of both CCD and CMOS processes  LCFI successfully demonstrated proof of principle in 2007 in ISIS1 and will submit next generation ISIS2 in May 2008

6. Andrei Nomerotski 6 The ISIS1  16x16 pixels, each 40x160  m 2  Five storage cells for pixel  Direct access to pixels by Row Select, no edge logic  Two variants : with and without p-well  Produced by e2V in UK u e2V had to rerun the p-well variant

7. Andrei Nomerotski 7 ISIS Proof of Principle  Tests with 55 Fe X-ray source u Demonstrated correct charge storage in 5 time slices and consequent readout K.Stefanov, RAL

8. Andrei Nomerotski 8 ISIS1 with p-well  High p-well doping protect storage register  Look at ratio R of charge collected at photogate to charge collected at storage pixel u From 55 Fe (1640 e-)  If increase clock voltage, get punchthrough under in- pixel CCD, R drops  Lower p-well doping, charge reflection decreases  No p-well, R ~ 7 u dependent on gate geometry and voltages K.Stefanov G.Zhang, RAL

9. Andrei Nomerotski 9 ISIS1 Testbeam  Constructed telescope with five ISIS1 chips u No p-well  Active area 0.56 x 2.22 mm 2 u Accurate alignment required  Tests performed at DESY 1-6 GeV electron beam in Nov 2007  Readout speed 2.5 MHz u ILC needs 1 MHz J.Veltius J.Goldstein S.Mandry, Bristol

10. Andrei Nomerotski 10 Test Beam First Results  S/N = 37  Position resolution in x- direction 10.8  m  Pitch 60  m  some charge sharing  Sqrt(60  m) = 17.3  m u Included large multiple scattering  Little charge sharing in y- direction (140  m across pixel)  Next testbeam in August at CERN u Large beam energy and EUDET telescope  Will test ISIS1 with p-well Correlation between measured and predicted position J.Veltius, Bristol

11. Andrei Nomerotski 11 Next generation ISIS: ISIS2  Jazz Semiconductor will manufacture ISIS2  Process: 0.18  m with dual gate oxide  possible voltages 1.8V and 5 V  p++ wafers with 25  m epi layer  > 100 Ohm cm u Area 1 cm 2 (four 5x5 mm 2 tiles)  Will develop buried channel and deep p+ implant u Buried channel is necessary for CCD u Non-overlapping gates u Deep p+ is beneficial to decouple buried channel from p-well, no need for punchthrough, was absent in ISIS1  Cross section under Photogate:

12. Andrei Nomerotski 12 ISIS2 Design  Pixels 80 x 10  m 2  Buried channel 5  m wide  3 metal layers  CCD gates: doped polysilicon  Logic, source follows use 5V custom logic gates

13. Andrei Nomerotski 13 ISIS2 Design  One chip will have several variants of ISIS2 u Each has independent control  Row select and decoder edge logic  Will have several test structures  Submission in May 2008 K.Stefanov P.Murray, RAL

14. Andrei Nomerotski 14 ISIS2 Variations  Reset transistor u Surface u Buried channel  Deep p+ u With deep p+ u Without deep p+ u With deep p+ but no charge collection hole u Change in dopant concentrations of ~20%  CCD gate width

15. Andrei Nomerotski 15 Charge Collection  Performance extensively simulated  Charge collection: K.Stefanov

16. Andrei Nomerotski 16 Charge transfer  Simulated charge transfer to photogate and to storage cells – all function with high efficiency K.Stefanov

17. Andrei Nomerotski 17 3D ISIS Concept  Discussed implementation of ISIS with MIT Lincoln Labs – one of the options was a 3D ISIS  3D ISIS has two Tiers u 1 st Tier : Storage (CCD) part u 2 nd Tier : Readout (CMOS) part  Zigzag CCD register controlled by linear gates  CCD clock distribution in CCD tier   A.Nomerotski K.Stefanov

18. Andrei Nomerotski 18 Summary  ISIS concept: pixels with storage in a mini CCD u Easier for light, difficult for particles  LCFI demonstrated proof of principle of ISIS in ISIS1 u Collection of charge through photogate u Shielding of CCD register by p-well u Tested in testbeam  Nest generation sensor ISIS2 should be available by the end of the year

19. Andrei Nomerotski 19 Backups

20. Andrei Nomerotski 20 ISIS1 Charge Collection  Charge is collected through a punchthrough in p-well