Presentation is loading. Please wait.

Presentation is loading. Please wait.

Hugo Furtado CERN - Microelectronics Group 11th Workshop on Electronics for LHC and future Experiments Delay25, an ASIC for timing adjustment in LHC Delay25.

Published byBlanche Skinner Modified over 8 years ago

Similar presentations

Presentation on theme: "Hugo Furtado CERN - Microelectronics Group 11th Workshop on Electronics for LHC and future Experiments Delay25, an ASIC for timing adjustment in LHC Delay25."— Presentation transcript:

1 Hugo Furtado CERN - Microelectronics Group 11th Workshop on Electronics for LHC and future Experiments Delay25, an ASIC for timing adjustment in LHC Delay25 An ASIC for timing adjustment in LHC CERN PH/MIC, Geneva Switzerland H. Furtado, A. Marchioro, P. Moreira and J. Schrader

2 Hugo Furtado CERN - Microelectronics Group 11th Workshop on Electronics for LHC and future Experiments Delay25, an ASIC for timing adjustment in LHC Outline Motivation ASIC Functionality and Architecture Measurements and results

3 Hugo Furtado CERN - Microelectronics Group 11th Workshop on Electronics for LHC and future Experiments Delay25, an ASIC for timing adjustment in LHC Objectives Timing Adjustment Self-Calibrated Radiation Tolerant

4 Hugo Furtado CERN - Microelectronics Group 11th Workshop on Electronics for LHC and future Experiments Delay25, an ASIC for timing adjustment in LHC Delay25 - Features 4 channel programmable CMOS delay line –Master channel: Calibration reference Clock signal Clock frequencies: –32, 40, 64 or 80 MHz –4 channels: (Non-)periodic digital signals Independently programmed –Channel phase: 0.5 ns resolution –I2C interface: ASIC control

5 Hugo Furtado CERN - Microelectronics Group 11th Workshop on Electronics for LHC and future Experiments Delay25, an ASIC for timing adjustment in LHC Delay25 - Features –0.25 µm CMOS technology –Radiation tolerant –Self calibrating –Phase resolution: 0.5 ns –Output jitter: < 19 ps (rms) –Integral non-linearity < 44 ps (rms) –Differential non-linearity < 35 ps (rms) –Configurable I/O: CMOS 2.5V LVDS –Supply voltage: 2.5 V –Package: TQFP32 –Power Consumption of 130 mW

6 Hugo Furtado CERN - Microelectronics Group 11th Workshop on Electronics for LHC and future Experiments Delay25, an ASIC for timing adjustment in LHC Delay25 - Layout

7 Hugo Furtado CERN - Microelectronics Group 11th Workshop on Electronics for LHC and future Experiments Delay25, an ASIC for timing adjustment in LHC Architecture

8 Hugo Furtado CERN - Microelectronics Group 11th Workshop on Electronics for LHC and future Experiments Delay25, an ASIC for timing adjustment in LHC DLL Architecture

9 Hugo Furtado CERN - Microelectronics Group 11th Workshop on Electronics for LHC and future Experiments Delay25, an ASIC for timing adjustment in LHC Speeding up and Slowing Down

10 Hugo Furtado CERN - Microelectronics Group 11th Workshop on Electronics for LHC and future Experiments Delay25, an ASIC for timing adjustment in LHC Replica Channels

11 Hugo Furtado CERN - Microelectronics Group 11th Workshop on Electronics for LHC and future Experiments Delay25, an ASIC for timing adjustment in LHC Getting the Delayed Signal

12 Hugo Furtado CERN - Microelectronics Group 11th Workshop on Electronics for LHC and future Experiments Delay25, an ASIC for timing adjustment in LHC Different Input Reference Frequencies

13 Hugo Furtado CERN - Microelectronics Group 11th Workshop on Electronics for LHC and future Experiments Delay25, an ASIC for timing adjustment in LHC Measurements -40MHz and at room temperature Functionality Integral and Differential Non-Linearity Jitter Crosstalk

14 Hugo Furtado CERN - Microelectronics Group 11th Workshop on Electronics for LHC and future Experiments Delay25, an ASIC for timing adjustment in LHC Functionality - CLK CMOSLVDS

15 Hugo Furtado CERN - Microelectronics Group 11th Workshop on Electronics for LHC and future Experiments Delay25, an ASIC for timing adjustment in LHC Integral Error - CLK CMOSLVDS Integral error rms: 41ps ; p-p: ±79ps Integral error rms: 41ps ; p-p: ±71ps

16 Hugo Furtado CERN - Microelectronics Group 11th Workshop on Electronics for LHC and future Experiments Delay25, an ASIC for timing adjustment in LHC Differential Error - CLK CMOSLVDS Differential error rms: 35ps ; p-p: ±100ps Differential error rms: 32ps ; p-p: ±84ps

17 Hugo Furtado CERN - Microelectronics Group 11th Workshop on Electronics for LHC and future Experiments Delay25, an ASIC for timing adjustment in LHC Integral Error : CH0 (LVDS) CLK CH0 Integral error rms: 43ps ; p-p: ±87ps Integral error rms: 41ps ; p-p: ±71ps

18 Hugo Furtado CERN - Microelectronics Group 11th Workshop on Electronics for LHC and future Experiments Delay25, an ASIC for timing adjustment in LHC Differential Error : CH0 (LVDS) CLKCH0 Differential error rms: 31ps ; p-p: ±84ps Differential error rms: 32ps ; p-p: ±84ps

19 Hugo Furtado CERN - Microelectronics Group 11th Workshop on Electronics for LHC and future Experiments Delay25, an ASIC for timing adjustment in LHC Pulse Width CH0: blue - rising edge, red – falling edgeCH0: measured width

20 Hugo Furtado CERN - Microelectronics Group 11th Workshop on Electronics for LHC and future Experiments Delay25, an ASIC for timing adjustment in LHC Jitter - CLK (CMOS) std dev = 15ps 40MHz clock - TAP 50

21 Hugo Furtado CERN - Microelectronics Group 11th Workshop on Electronics for LHC and future Experiments Delay25, an ASIC for timing adjustment in LHC Jitter - CLK (LVDS) std dev = 15ps 40MHz clock - TAP 50 Gen: 8 ns

22 Hugo Furtado CERN - Microelectronics Group 11th Workshop on Electronics for LHC and future Experiments Delay25, an ASIC for timing adjustment in LHC Jitter – CH0 (LVDS) std dev = 18ps 40MHz clock - TAP 50 Gen: 8 ns

23 Hugo Furtado CERN - Microelectronics Group 11th Workshop on Electronics for LHC and future Experiments Delay25, an ASIC for timing adjustment in LHC Influence of crosstalk on Jitter Input signal correlated with the clock std dev = 18ps 40MHz clock - CH0 - TAP 50 Gen: 8 ns

24 Hugo Furtado CERN - Microelectronics Group 11th Workshop on Electronics for LHC and future Experiments Delay25, an ASIC for timing adjustment in LHC Influence of crosstalk on Jitter std dev = 19ps Input signal not correlated with the clock 40MHz clock - CH0 - TAP 50 Gen: 8 ns

25 Hugo Furtado CERN - Microelectronics Group 11th Workshop on Electronics for LHC and future Experiments Delay25, an ASIC for timing adjustment in LHC Integral Error: Crosstalk CH0 (w/crosstalk from CH1 - correlated) Integral error - Correlated crosstalk rms:42ps ; p-p: ±70ps Integral error - Clk no crosstalk rms: 41ps ; p-p: ±71ps Integral error - CH0 no crosstalk rms: 41ps ; p-p: ±71ps

26 Hugo Furtado CERN - Microelectronics Group 11th Workshop on Electronics for LHC and future Experiments Delay25, an ASIC for timing adjustment in LHC Differential Error: Crosstalk CH0 (w/crosstalk from CH1 - correlated) Differential error - Correlated Crosstalk rms: 32ps ; p-p: ±83ps Differential error - Clk rms: 32ps ; p-p: ±84ps Differential error – CH0 w/o crosstalk rms: 31ps ; p-p: ±84ps

27 Hugo Furtado CERN - Microelectronics Group 11th Workshop on Electronics for LHC and future Experiments Delay25, an ASIC for timing adjustment in LHC Integral Error: Crosstalk CH0 (w/crosstalk from CH1 - not correlated) Integral error - Non Correlated Crosstalk rms43ps ; p-p: ±75ps Integral error - Clk rms: 41ps ; p-p: ±71ps Integral error – CH0 w/o crosstalk rms: 41ps ; p-p: ±71ps

28 Hugo Furtado CERN - Microelectronics Group 11th Workshop on Electronics for LHC and future Experiments Delay25, an ASIC for timing adjustment in LHC Differential Error: Crosstalk CH0 (w/crosstalk from CH1 – not correlated) Differential error - Non Correlated Crosstalk rms: 34ps ; p-p: ±87ps Differential error - Clk rms: 32ps ; p-p: ±84ps Differential error – CH0 w/o crosstalk rms: 31ps ; p-p: ±84ps

29 Hugo Furtado CERN - Microelectronics Group 11th Workshop on Electronics for LHC and future Experiments Delay25, an ASIC for timing adjustment in LHC Electrical Characteristics Power Consumption: 130 mW Lock range in the 40 MHz mode: 25-80 MHz Supply Voltage Range: 2.2-2.8 V

30 Hugo Furtado CERN - Microelectronics Group 11th Workshop on Electronics for LHC and future Experiments Delay25, an ASIC for timing adjustment in LHC Conclusions -The Delay 25 has been fabricated in the 0.25 µm CMOS technology -Self calibrating -Independently programmable 4 channel with 0.5ns resolution -Performance has been evaluated -Correct functional behaviour -Jitter < 19 ps (rms) -Integral Error < 44 ps (rms) -Differential Error < 35 ps (rms) -Power Consumption: 130 mW -Cost ~10 CHF -More Tests Scheduled -Characterization at all frequencies -Radiation

Download ppt "Hugo Furtado CERN - Microelectronics Group 11th Workshop on Electronics for LHC and future Experiments Delay25, an ASIC for timing adjustment in LHC Delay25."

Similar presentations

Potentialities of common-used TDC chips for high-speed event timer design E. Boole, V. Vedin Institute of Electronics and Computer Science, Riga, Latvia.

Potentialities of common-used TDC chips for high-speed event timer design E. Boole, V. Vedin Institute of Electronics and Computer Science, Riga, Latvia.
Large Area, High Speed Photo-detectors Readout Jean-Francois Genat + On behalf and with the help of Herve Grabas +, Samuel Meehan +, Eric Oberla +, Fukun.

Large Area, High Speed Photo-detectors Readout Jean-Francois Genat + On behalf and with the help of Herve Grabas +, Samuel Meehan +, Eric Oberla +, Fukun.
Motivation Yang You 1, Jinghong Chen 1, Datao Gong 2, Deping Huang 1, Tiankuan Liu 2, Jingbo Ye 2 1 Department of Electrical Engineering, Southern Methodist.

Motivation Yang You 1, Jinghong Chen 1, Datao Gong 2, Deping Huang 1, Tiankuan Liu 2, Jingbo Ye 2 1 Department of Electrical Engineering, Southern Methodist.
Development of a 20 GS/s Sampling Chip in 130nm CMOS Technology Jean-Francois Genat On behalf of Mircea Bogdan 1, Henry J. Frisch 1, Herve Grabas 3, Mary.

Development of a 20 GS/s Sampling Chip in 130nm CMOS Technology Jean-Francois Genat On behalf of Mircea Bogdan 1, Henry J. Frisch 1, Herve Grabas 3, Mary.
A Serializer ASIC for High Speed Data Transmission in Cryogenic and HiRel Environment Tiankuan Liu On behalf of the ATLAS Liquid Argon Calorimeter Group.

A Serializer ASIC for High Speed Data Transmission in Cryogenic and HiRel Environment Tiankuan Liu On behalf of the ATLAS Liquid Argon Calorimeter Group.
An Ultra Low Power DLL Design

An Ultra Low Power DLL Design
CARIOCA (Cern and RIO Current Amplifier). The CARIOCA chip has 8 binary output, therefore DIALOG has 16 PCH as input channels and has up to 8 LCH as output.

CARIOCA (Cern and RIO Current Amplifier). The CARIOCA chip has 8 binary output, therefore DIALOG has 16 PCH as input channels and has up to 8 LCH as output.
Filip Tavernier Karolina Poltorak Sandro Bonacini Paulo Moreira

Filip Tavernier Karolina Poltorak Sandro Bonacini Paulo Moreira
Design of a 10 Bit TSMC 0.25μm CMOS Digital to Analog Converter Proceedings of the Sixth International Symposium on Quality Electronic Design IEEE, 2005.

Design of a 10 Bit TSMC 0.25μm CMOS Digital to Analog Converter Proceedings of the Sixth International Symposium on Quality Electronic Design IEEE, 2005.
Leo Greiner IPHC meeting 2008-04-031 HFT PIXEL DAQ Prototype Testing.

Leo Greiner IPHC meeting HFT PIXEL DAQ Prototype Testing.
K.C.RAVINDRAN,GRAPES-3 EXPERIMENT,OOTY 1 Development of fast electronics for the GRAPES-3 experiment at Ooty K.C. RAVINDRAN On Behalf of GRAPES-3 Collaboration.

K.C.RAVINDRAN,GRAPES-3 EXPERIMENT,OOTY 1 Development of fast electronics for the GRAPES-3 experiment at Ooty K.C. RAVINDRAN On Behalf of GRAPES-3 Collaboration.
Delay Locked Loop with Linear Delay Element

Delay Locked Loop with Linear Delay Element
September 8-14, 20027 th Workshop on Electronics for LHC1 Channel Control ASIC for the CMS Hadron Calorimeter Front End Readout Module Ray Yarema, Alan.

September 8-14, th Workshop on Electronics for LHC1 Channel Control ASIC for the CMS Hadron Calorimeter Front End Readout Module Ray Yarema, Alan.
A Low-Jitter 8-to-10GHz Distributed DLL for Multiple-Phase Clock Generation Keng-Jan Hsiao and Tai-Cheng Lee National Taiwan University Taipei, Taiwan.

A Low-Jitter 8-to-10GHz Distributed DLL for Multiple-Phase Clock Generation Keng-Jan Hsiao and Tai-Cheng Lee National Taiwan University Taipei, Taiwan.
Design studies of a low power serial data link for a possible upgrade of the CMS pixel detector Beat Meier, Paul Scherrer Institut PSI TWEPP 2008.

Design studies of a low power serial data link for a possible upgrade of the CMS pixel detector Beat Meier, Paul Scherrer Institut PSI TWEPP 2008.
9 th Workshop on Electronics for LHC Experiments 2 October 2003 P. Antonioli (INFN/Bologna) A 20 ps TDC readout module for the Alice Time of Flight system:

9 th Workshop on Electronics for LHC Experiments 2 October 2003 P. Antonioli (INFN/Bologna) A 20 ps TDC readout module for the Alice Time of Flight system:
The DRS2 Chip: A 4.5 GHz Waveform Digitizing Chip for the MEG Experiment Stefan Ritt Paul Scherrer Institute, Switzerland.

The DRS2 Chip: A 4.5 GHz Waveform Digitizing Chip for the MEG Experiment Stefan Ritt Paul Scherrer Institute, Switzerland.
FED RAL: Greg Iles5 March 20031 The 96 Channel FED Tester What needs to be tested ? Requirements for 96 channel tester ? Baseline design Functionality.

FED RAL: Greg Iles5 March The 96 Channel FED Tester What needs to be tested ? Requirements for 96 channel tester ? Baseline design Functionality.
1 A High-Speed and Wide Detectable Frequency Range Phase Detector for DLLs Babazadeh, H.; Esmaili, A.; Hadidi, K.; NORCHIP, 2009 Digital Object Identifier:

1 A High-Speed and Wide Detectable Frequency Range Phase Detector for DLLs Babazadeh, H.; Esmaili, A.; Hadidi, K.; NORCHIP, 2009 Digital Object Identifier:
A high speed serializer ASIC for ATLAS Liquid Argon calorimeter upgrade Tiankuan Liu On behalf of the ATLAS Liquid Argon Calorimeter Group Department of.

A high speed serializer ASIC for ATLAS Liquid Argon calorimeter upgrade Tiankuan Liu On behalf of the ATLAS Liquid Argon Calorimeter Group Department of.

Similar presentations

Ads by Google