1. Microelectronic Circuit Design McGraw-Hill Chapter 4 Field-Effect Transistors Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock

2. Microelectronic Circuit Design McGraw-Hill MOS Capacitor Structure First electrode- Gate: Consists of low-resistivity material such as metal or polycrystalline silicon Second electrode- Substrate or Body: n- or p-type semiconductor Dielectric-Silicon dioxide:stable high-quality electrical insulator between gate and substrate.

3. Microelectronic Circuit Design McGraw-Hill Substrate Conditions for Different Biases Accumulation – V G <<V TN Depletion – V G <V TN Inversion – V G >V TN Accumulation Depletion Inversion

4. Microelectronic Circuit Design McGraw-Hill Low-frequency C-V Characteristics for MOS Capacitor on P-type Substrate MOS capacitance is non- linear function of voltage. Total capacitance in any region dictated by the separation between capacitor plates. Total capacitance modeled as series combination of fixed oxide capacitance and voltage-dependent depletion layer capacitance.

5. Microelectronic Circuit Design McGraw-Hill NMOS Transistor: Structure 4 device terminals: Gate(G), Drain(D), Source(S) and Body(B). Source and drain regions form pn junctions with substrate. v SB, v DS and v GS always positive during normal operation. v SB always < v DS and v GS to reverse bias pn junctions

6. Microelectronic Circuit Design McGraw-Hill NMOS Transistor: Qualitative I-V Behavior V GS <<V TN : Only small leakage current flows. V GS <V TN : Depletion region formed under gate merges with source and drain depletion regions. No current flows between source and drain. V GS >V TN : Channel formed between source and drain. If v DS >0,, finite i D flows from drain to source. i B =0 and i G =0.

7. Microelectronic Circuit Design McGraw-Hill NMOS Transistor: Triode Region Characteristics where, K n = K n ’W/L K n ’=  n C ox ’’ (A/V 2 ) C ox ’’=  ox /T ox  ox =oxide permittivity (F/cm) T ox= oxide thickness (cm) for

8. Microelectronic Circuit Design McGraw-Hill NMOS Transistor: Triode Region Characteristics (contd.) Output characteristics appear to be linear. FET behaves like a gate-source voltage- controlled resistor between source and drain with

9. Microelectronic Circuit Design McGraw-Hill MOSFET as Voltage-Controlled Resistor Example 1: Voltage-Controlled Attenuator To maintain triode region operation, or If K n =500  A/V 2, V TN =1V, R=2k  and V GG =1.5V, then,

10. Microelectronic Circuit Design McGraw-Hill MOSFET as Voltage-Controlled Resistor (contd.) Example 2: Voltage-Controlled High-Pass Filter Voltage Transfer function, where, cut-off frequency If K n =500  A/V 2, V TN =1V, C=0.02  F and V GG =1.5V, then, To maintain triode region operation,

11. Microelectronic Circuit Design McGraw-Hill NMOS Transistor: Saturation Region If v DS increases above triode region limit, channel region disappears, also said to be pinched-off. Current saturates at constant value, independent of v DS. Saturation region operation mostly used for analog amplification.

12. Microelectronic Circuit Design McGraw-Hill NMOS Transistor: Saturation Region (contd.) for is also called saturation or pinch-off voltage

13. Microelectronic Circuit Design McGraw-Hill Transconductance of a MOS Device Transconductance relates the change in drain current to a change in gate-source voltage Taking the derivative of the expression for the drain current in saturation region,

14. Microelectronic Circuit Design McGraw-Hill Channel-Length Modulation As v DS increases above v DSAT, length of depleted channel beyond pinch-off point,  L, increases and actual L decreases. i D increases slightly with v DS instead of being constant.  channel length modulation parameter

15. Microelectronic Circuit Design McGraw-Hill Depletion-Mode MOSFETS NMOS transistors with Ion implantation process used to form a built-in n-type channel in device to connect source and drain by a resistive channel Non-zero drain current for v GS =0, negative v GS required to turn device off.

16. Microelectronic Circuit Design McGraw-Hill Transfer Characteristics of MOSFETS Plots drain current versus gate-source voltage for a fixed drain-source voltage

17. Microelectronic Circuit Design McGraw-Hill Body Effect or Substrate Sensitivity Non-zero v SB changes threshold voltage, causing substrate sensitivity modeled by where V TO = zero substrate bias for V TN (V)  body-effect parameter   F = surface potential parameter (V)

18. Microelectronic Circuit Design McGraw-Hill Enhancement-Mode PMOS Transistors: Structure P-type source and drain regions in n-type substrate. v GS <0 required to create p-type inversion layer in channel region For current flow, v GS< v TP To maintain reverse bias on source-substrate and drain- substrate junctions, v SB <0 and v DB <0 Positive bulk-source potential causes V TP to become more negative

19. Microelectronic Circuit Design McGraw-Hill Microelectronic Circuit Design McGraw-Hill Enhancement-Mode PMOS Transistors: Output Characteristics For, transistor is off. For more negative v GS, drain current increases in magnitude. PMOS is in triode region for small values of V DS and in saturation for larger values.

20. Microelectronic Circuit Design McGraw-Hill MOSFET Circuit Symbols (g) and(i) are the most commonly used symbols in VLSI logic design. MOS devices are symmetric. In NMOS, n + region at higher voltage is the drain. In PMOS p + region at lower voltage is the drain

21. Microelectronic Circuit Design McGraw-Hill Process-defining Factors Minimum Feature Size, F : Width of smallest line or space that can be reliably transferred to wafer surface using given generation of lithographic manufacturing tools Alignment Tolerance, T: Maximum misalignment that can occur between two mask levels during fabrication

22. Microelectronic Circuit Design McGraw-Hill Mask Sequence for a Polysilicon-Gate Transistor Mask 1: Defines active area or thin oxide region of transistor Mask 2: Defines polysilicon gate of transistor, aligns to mask 1 Mask 3: Delineates the contact window, aligns to mask 2. Mask 4: Delineates the metal pattern, aligns to mask 3. Channel region of transistor formed by intersection of first two mask layers. Source and Drain regions formed wherever mask 1 is not covered by mask 2

23. Microelectronic Circuit Design McGraw-Hill Basic Ground Rules for Layout F=2  T=F/2=  could be  1, 0.5, 0.25  m, etc.