1. 1 PRESTO Modeling Alessandro Arnulfo R&D Application Engineer

2. 2 PRESTO Modeling

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5. 5 CMOS Driver PRESTO Modeling

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10. 10 FILE_TYPE=HDT_PLIB; TIME=Fri May 31 11:19:52 1996 COMPONENT=ACT240; FAMILY=DEFAULT; PACKAGE=DEFAULT,DIP20,SOIC20,PLCC20; FACTORY=DEFAULT; TYPE= IC; NPINS=20; BEGIN_PIN FACT_RCT_P=1,2,3,4,5,6,7,8,9,11,12,13,14,15,16,17,18,19; FACT_3S24_P=3,5,7,9,12,14,16,18; FACT_GND_P=10; FACT_VCC_P=20; END_PIN; BEGIN_FUNCTION RECEIVER=1,2,4,6,8,11,13,15,17,19; 3STATE=3,5,7,9,12,14,16,18; POWER=10,20; END_FUNCTION; BEGIN_POWER GND1=10,ALL; POW1=20,ALL; END_POWER; BEGIN_CLASS DEFAULTCMOS=1,2,3,4,5,6,7,8,9,11,12,13,14,15,16,17,18,19; DEFAULTGND=10; DEFAULTVCC=20; END_CLASS; BEGIN_DR_LIST FACT_3S24_P; END_DR_LIST; END. S_MODEL = PACKAGE; DESCRIPTION = DIP16 pin; BEGIN_SUBCKT ************** DIP16 model ****.SUBCKT DIP16 1 3 * 1=input, output=2, LR model, date:13 Jan 1993 R1 3 2 500 L1 3 2 3.5N L2 2 1 2.5N.ENDS DIP16 ************ END_SUBCKT PRESTO Modeling

11. 11 S_MODEL = 3STATE; DESCRIPTION = FACT 3-state 24mA driver ; RISE_DRVR_DELAY= 1.25 ; FALL_DRVR_DELAY= 1.25 ; BEGIN_SUBCKT *************** FACT 3STATE MODEL *********** * creation date: 19 Jan 1993 * * maximum simulation time step: 100ps * recommended simulation time step <= 50ps * ideal logic input stimulus (0 1) *********************************************.SUBCKT FACT_3S24 1 2 10 20 * in out VCC GND * output capacitance COUT 2 0 15P * 0-1 waveform RSWVCC 7 2 1 0 PWL(0V 1E6 1V 1E-02 2V 1E-02) C=2P PVCC 7 8 -5V -141MA -4V -140MA -3V -130MA -640MV -50MA 0 0 + 350MV 52MA C=3P E1 8 9 1 0 s(t)=PWL (0.0 0 1.7N 1) THR(.5V 0 5).1N VCOMP 10 9 DC(5) * 1-0 waveform RSWGND 17 2 1 0 PWL(-1V 1E-02 0V 1E-2 1V 1E6) C=2P PGND 17 18 -2.6V -170MA -1.8V -162MA -0.5V -93MA 0 0 1.2V 140MA + 3V 170MA 5V 175MA C=3P E0 18 19 1 0 s(t)=PWL (0.0 0 1.7N 1) THR(.5V 0 5).1N TDECOUP 19 20 C=6P.ENDS FACT_3S24 ********************************************* END_SUBCKT S_MODEL = DRIVER; DESCRIPTION = FACT 24mA driver with package; RISE_DRVR_DELAY= 1.18 ; FALL_DRVR_DELAY= 1.18 ; BEGIN_SUBCKT *************** FACT PACKAGED DRIVER MODEL *********** * creation date: 19 Jan 1993 * * maximum simulation time step: 100ps * recommended simulation time step <= 50ps * ideal logic output signal (0 1) *********************************************.SUBCKT FACT_DR24_P 1 2 10 20 * in out VCC GND * power package and dynamic behavior XVCC 10 11 $P1 XGND 20 21 $P1 XCOMP 1 2 11 21 FACT_DR24.ENDS FACT_DR24_P ****************** END_SUBCKT PRESTO Modeling