1. DWS : Digital Wave Simulator

2. DWS simulator Spice-like syntax DSP based

3. Primitives Linear R,L,C Trasmission lines Mutual inductors Ideal transformers Adaptors (series, bimodal, n-modal) Non linear resistors Time controlled resistor Voltage controlled resistors Independent sources Voltage/current controlled sources Time-domain scattering parameters Spice-like.model (Diode, BJT)

4. Resistors, Capacitors and Inductors Resistor: an active power load (positive sign) or generator (negative sign) Inductor: a reactive power “storage” Capacitor: a reactive power storage

5. Non-Linear Resistors Linear resistor V I V/I = R (constant) Non-linear resistor V I V/I = V I v1 i1 v2 i2 v3 i3 …... Non-linear resistors can show a non-monotone shape and a no-crossing zero behaviour Non-linear resistors are widely used to describe clamping diode or driver’s pull-up/pull-down transistors Pxxxx 1 2 -5V -10mA -3V -1mA -0.5V -0.1mA 0V 0A 1V 10mA 2V 100mA Z0=value C= value L=value

6. Mutual Inductors

7. Controlled Voltage/Currents Sources (1) Example 1: simple 5V voltage source controlled by a 3.3V input ( with linear 30ohm output impedance ) Vxxxx 20 0 10 0 s(t)=PWL(0 0 1ns 1v 1.5ns 1.2v 2ns.9v 3ns 1) THR(1.5 0 5) 3N 30 The control chain must be applied starting from the end: 1) Delay, 2) static transfer function, 3) dynamic transfer function in this case: Vout Vin t s(t) 1 3N Vth DELAY Static Transfer Function Dynamic Transfer Function t Vin 3.3 t Vin 3.3 3n t 5 t 5

8. Controlled Voltage/Currents Sources(2) Static and dynamic characteristics order is very important: a complete different result is obtained if the order is reversed: Vxxxx 10 0 20 0 THR(1.5 0 5) s(t)=PWL(0 0 1ns 1v 1.5ns 1.2v 2ns.9v 3ns 1) 3N 30 The control chain must be applied starting from the end: 1) Delay, 2) dynamic transfer function, 3) static transfer function in this case: 3N Vout Vin Vth DELAY Static Transfer Function t s(t) 1 Dynamic Transfer Function t Vin 3.3 t Vin 3.3 3n t 3.3 3n t 5

9. Controlled Voltage/Currents Sources(3) Application: Starting from a “0-1 logic level” bit sequence create a “5V” signal with a jitter that is a function of the intersymbol interference Vstim 1 0 PULSE(0 1 0 100P 100P 10N 10N) PSEQ(01001011101000001001111101110001100111111011110011000010010) Einterference 2 0 1 0 THR(0.5 0 1) s(t)=PWL(0 0 1N 0.4.4 10N 0.8 25N 0.95 60N 1) Eout 3 0 2 0 s(t)=PWL(0 0 0.4N 0.15 1.5N 0.9 2N 1.2 2.5N 1.3 3N 0.8 4N 1.1 5N 1) 5 Rout 3 4 20 Cout 4 0 10P Node 1 (input pattern) Node 4 (output pattern)

10. Voltage/Current Controlled Resistors(1).SUBCKT LV_DR4_4 1 2 10 20 * in out VCC GND * output capacitance Cout2 0 7pf * pull-up Rsw1 7 2 1 0 PWL(0V 1e6.2 10K.3 2K.4 1K 0.5V 300.6 250.7 150.8 100.9 40 1V.1 2V.1 ) Pvcc 7 10 -3.3V -25mA -2V -23mA -1V -18mA 0 0 1V 0 C=.2P * pull-down Rsw2 17 2 1 0 PWL(-1V.1 0V.1.1 40.2 100.3 150.4 250.5V 300.6 1K.7 3K.8 10K 1V 1e6) Pgnd 17 20 -1V 0 0V 0 1V 18mA 2V 23mA 3.3V 25mA.ENDS LV_DR4_4 in out vcc gnd out (2) vcc (10) gnd (20) in (1) out (2) Cout Pvcc Pgnd Rsw1 Rsw2

11. Voltage/Current Controlled Resistors(2) Vgs Vds Ids Vds Ids B2 B3 B1 C A Vgs=5V Vgs=4V Vgs=3V Vgs=2V 1 2 3 4 t Vds 3 2 1 A C C C B Rise times of Vgs Vds Ids C A Vgs=5V Vgs=4V Vgs=3V Vgs=2V 1 2 3 4 t Vds 1 2 3 A C C C B Rise time of Vgs B3 B2 B1

12. Voltage/Current Controlled Resistors(3) Rsw1 Rsw2 Gnd Vcc Moving up and down the characteristics modify the unloaded output rise/fall times The PWL shapes modify the trajectories on the V/I output graph The speed (and shape) of the Vgs transitions have influence on the unloaded output rise/fall times Vgs The central section of the characteristics influences the feed- through current