1. Digital and Analog signal

2. New Trends Clock Speed (MHz) 1988 1990 1992 1994 1996 1998 2000 200 100 50 25 Bus Width (bits) 128 64 32 16 8

3. Technology Evolution

4. Digital signal Problems Single net Multiple net Reflection EMC radiation Stub ringing Jitter Losses Crosstalk SSN Power supply distribution noise Clock tree skew EMC radiation

5. Rise/Fall times (T r,T f ) Multi-crossing threshold High level overshoot (V ov ) Low level oveshoot Ringing Static levels Level references (V ih, Vil) Waveform Parameters

6. When to Worry About SI T r > T pd Multi-pin connectors Wide buses Heavily loaded lines Loads concentrated Buses cannot be terminated New, unproven devices Critical timing

7. Analysis Tool Be careful : you can spend 2 days or 2 months for the analysis Analyze and understand criteria and analysis tools Identify the potential problem areas Measure new phenomena / technologies (Oscilloscope, TDR, Network analyzer) Domains: Time domain and Frequency Domain

8. This definition apply at any interconnection level: Within chips (Leadframes) Between components (PCB traces) Between boards (Connectors) Between subsystems (Cables) Transmission Line

9. Resistance per Unit Length Inductance per Unit Length Capacitance per Unit Length Conductance per Unit Length Lossless case: R = 0, G = 0 Transmission Line

10. Physical description thickness width length crossection Electrical characteristics Z0 (impedance) Tpd (delay) loss

11. Transmission Line Characteristics

12. Voltage and Current Waves V(x,t) = Vi + Vr I(x,t) = Ii + Ir 1) For the first waveform, the transmission line shows its line impedance 2) The incident wave travels down the line. After Tpd time, the waveform hits the load, and a portion of the wave is reflected. 3) The reflected wave travels down the line. After Tpd time, the waveform hits the source, and a portion of the wave is reflected.

13. Definition: Special cases: when Z = Z0 (matched impedance) when Z = infinite (open circuit) when Z = 0 (short circuit ) Reflection Coefficient

14. normalembedded Conductor dielectric reference plane Disadvantages: nonhomogeneous medium (far- end crosstalk) Potential EMC problems Advantages: Faster than strip-lines Good for higher impedance Propagation speed is reduced of a factor Microstrips (normal and embedded)

15. normal Disadvantages: Slower than microstrip Advantages: Homogeneous medium (no far- end crosstalk) Reduced EMC problems Good for lower impedance Good for balanced signals (dual offset) dual offset Propagation speed is reduced of Striplines

16. Crosstalk is coupling of unwanted energy (signal) onto a victim line Coupling among TL (coupled lines in PCBs/leadframes/cables) Impedance of common current returns paths (Ground bounce) Coupling in connectors Indirect electromagnetic coupling (EMC) In this document crosstalk will refer to the direct coupling mechanism only (coupled lines in PCB/leadframe/cables and connectors) For each signal there is a “noise budged” allowed. All previous phenomena contribute to this budged What-is Crosstalk

17. Clock signals Long address / data buses Analog signals in digital circuits Asynchronous Signals (reset, etc) The configurations could be very complex where more signals can contribute to total crosstalk noise. For example: Ground signal Analog signal (victim) Clock signal (aggressor) Reset signal (victim) Read/Write signal (aggressor) Data signal(aggressor) Sensitive Signal Lines

18. A single line presents a very simple electromagnetic field configuration In general: a multi-conductor system of n conductors (excluding the reference conductor) shows n propagation modes. Two coupled lines show a more complex electromagnetic field configuration. There are two propagation modes and two propagation speeds. Electrical (green) and magnetic (blue) fields Electrical fields for even (left) and odd (right) for conductor A (magnetic field is omitted for simplicity) A B Parallel Trace Crosstalk

19. I c - I l RtRt cmcm lmlm RtRt RtRt RtRt x I c + I l Far-end crosstalk Near-end crosstalk ToTo 2T o T r +2 T TrTr T r + T reflection Case study: two-line symmetrical: two propagation MODEs (odd and even) homogeneous material -> Far-end crosstalk = 0 R t = termination resistor T r = rise time of the incident wave T o = propagation delay of the odd mode T e = propagation delay of the even mode T = difference between even and odd propagation delays Note: R t is calculated in order to match the impedance of the coupled structure to reduce reflections B A CD A B C D

20. Far-End Crosstalk RtRt cmcm lmlm RtRt RtRt RtRt x B A CD Far-end crosstalk ToTo TrTr T r + T A B C D The amplitude is a function of the coupling coefficient, but could be is “clamped” if the rise time is larger than the difference between the propagation delays of the two modes. At least, the amplitude can be 0 if the two modes propagates at same speed (case homogeneous material) Far-end crosstalk between two lines with an input signal of 200ps versus  T  T=0p Rise time=200p  T=50p  T=100p  T=150p  T=200p  T=250p  T=300p

21. RtRt cmcm lmlm RtRt RtRt RtRt x B A CD Near-end crosstalk 2T o T r +2 T TrTr A B C D Amplitude is only a function of the coupling coefficient. Near-end crosstalk between two lines with an input signal of 200ps versus  T (50ps step) TT 0 300ps Near-End Crosstalk

22. Incident and Transmitted Pulses RtRt cmcm lmlm RtRt RtRt RtRt x B A CD TrTr A B C D The transmitted pulse shows first an amplitude reduction due to loss of energy coupled to line CD. The incident waveform shows some reflections of the far-end crosstalk due to the different velocity of the propagation modes Reflection

23. Models for Crosstalk Marx, modale, generatori???

24. When the total length of the interconnection is long enough to be transmissive. With the actual technologies, length could be very short LS70 cm A, ALS25 cm FAST, FACT, ACT, AC, AS, BCT, LV15 cm ECLinPS3 cm When Use Termination

25. Matched Termination is possible if: Single path, no branches, no loads (Not practical) Matched source Matched load Reflections are eliminated at the far end of the signal path BUT: Signal level is cut down by half (only point to point) High driver/return current and power dissipation Matched Termination

26. The effective line impedance is defined by a combination of: The unloaded line impedance The effect of stubs (Zeff decrease) The effect of loads (Zeff decrease), usually capacitive. Starting from a unloaded line of about 100 ohms it is normal to obtain an effective impedance of 25-60ohm Effective Line Inpedance

27. ??? Vt Rt Rt = Z0 Rt > Z0 Z0, Td Vih Vil Usually: or : termin

28. Eye diagrams are obtained by superimposing all the time frames of a bit-sequence. This function is very useful to check the quality of a data transmission channel. Usually, this function requires the definition of stimulus signals with long bit-sequences Eye openingJitter Eye-diagram

29. Data detection is synchronized by the clock signal, that defines the bit-width. clock data Bit width Eye-diagram

30. Consider a waveform at receiver for a single edge signal Z0, Td t setup Inter-symbol interference occurs when: bit_width < t setup t setup is the settling time required to extinguish the transient. Example: settling time t setup = 11 ns 1) 200Mb/s bit-rate 5ns bit-width 3 bits (11/5) of inter-symbol interference 2) 500mb/s bit-rate 2ns bit-width 6 bits (11/2) of inter-symbol interference Note: previous bits could be 0 or 1. There are a lot of possible combinations pseudo-random bit sequences Inter-symbol interference

31. Eye-diagrams examples (1) This eye-diagram shows a bounce in the middle of the bit-time due to a mismatch of impedance that produce a noise margin reduction on signal levels in a critical point. The rise waveform shows a sliced edge due to the inter- symbolic interference This eye-diagram shows a strong jitter mainly due to the asymmetry between the “1” logic and the “0” logic bit widths

32. Eye-diagrams examples (2) Both eye-diagrams show a defect due to the rise and fall edges. The one on left shows a slow edge compared to the data transmission speed and the one on the rights shows non-monotone rising/falling edges.

33. Eye-diagram measurements are performed by oscilloscopes. Data Trigger in in DSO Signal under test Clock signal Common functions available on DSO: persistence jitter statistical distribution Bit-sequence: the actual bit-sequence of the system (in laboratory: a pseudo-random bit-sequence) Measuring Eye-diagrams

34. Simulated eye-diagram are obtained starting from simulations with long bit-sequences But: Which sequence? (PRBS, exhaustive?) How many bits generate significant inter-symbol interference? (strong impact on simulation time) Long simulation time Example: if the interconnection causes significant inter-symbol interference for 6 bits, an exhaustive analysis requires a bit-sequence containing 2 6 combinations (000000, 000001, 000010, …, 111111). The total sequence will be 64 x 6 = 384 bits long. If each bit is 10ns (100Mbit/s), the total simulation time will be about 4us. Simulating Eye-diagrams

35. Analytical procedure that starting from a single edge simulation evaluates: the eye-diagram with the worst-case inner envelope (minimum eye opening) the related worst-case bit-sequence t setup t bit Hypothesis: linear behavior of the system Worst-case Eye-diagram

36. 1) single step response chosen by the user: could be rise or fall characterized by a t setup and N samples t sample =T setup /(N samples - 1) t setup Basic principle to calculate it: Worst-case Eye-diagram

37. 2) bit-rate definition: defines the t bit defines the number of bits that generate interference (N bits = t setup /t bit ) t setup Worst-case Eye-diagram

38. 3) Previous bits contribution (case Nbits =1): Hyp: Previous bit 0->1 Hyp: Previous bit 1->0 Actual bit (stand alone) Actual bit (with distortion due to previous bits) For each sample of the waveform the contribution due to the sample of the previous bit (at one tbit of distance) must be added. Depending of the previous bit transition (0->1 or 1->0) the contribution can affect the inner or outer envelope Worst-case Eye-diagram

39. 4) Previous bits construction (case Nbits =3): t sample Worst case for upper inner envelope: 001 Worst case for lower inner envelope: 110 Worst case for upper inner envelope: 011 Worst case for lower inner envelope: 100 Note: The T bit is rounded on a integer number of T sample during the calculation t bit The worst case in calculated looking for the bit transition that gives the contribution in the same direction Current bit Worst-case Eye-diagram

40. 5) Worst case bit-sequence length optimization (case Nbits =3): 111 101 001 111 011 010 110 110 000 010 110 000 100 101 001 001 For each sample, there is a specific worst case combination. Of course there are duplications that can be deleted Same combination Worst-case Eye-diagram

41. 6) Worst case bit-sequence length optimization (case Nbits =3): 000 111 000 101 000 001 000 011 000 010 000 110 111 000 111 010 111 110 111 100 111 101 111 001 The worst-case bit-sequence is given by the sum of the single combinations. Because the calculation is performed with the hypothesis that the three-bit contribution is “pure”, no other transient queues must be present between the single combinations. This is obtained by adding additional 000 and 111 between one combination and the other. 111 101 001 111 011 010 110 110 000 010 110 000 100 101 001 001 Worst-case Eye-diagram

42. 7) Worst case bit-sequence for n-receiver interconnection Z0, Td 111 101 001 000 010 110 101 100 001 010 011 110 111 101 000 010 Each receiver has his worst-case bit-sequences that must be jointed. Redundancies can be deleted 000 111 000 101 000 001 000 100 111 000 111 010 111 110 111 011 Worst-case bit-sequence of the interconnection Worst-case Eye-diagram

44. TDR/TDT Basics TDR: Time Domain Reflectometry TDT: Time Domain Transmission –A voltage step is propagated down the transmission line under investigation, and the incident and reflected voltage waves are monitored by the oscilloscope at a particular point on the line Step-wave generator Oscilloscope DUT Launch cable (Z0) TDT TDR

45. TDR: Resolution two discontinuities become indistinguishable when separated by a time (and related distance) that is less than half of the risetime Example of two discontinuities 2mm apart. They can be distinguished only with a 10ps risetime

46. Multiple discontinuities  1 % error in  2 0.01 <.25%.05 ~ 2%.10 ~ 6% The first discontinuity has a maximum reflection coefficient of  1 and the second of  2. The table shows that the percent error in  2 due to  1 could be very high also for small value of  1. The first discontinuity causes a degradation of rise time and loss of accuracy on the second discontinuity

47. Normalization

48. TDR Amplitude Normally 250-400mV Some characterizations require smaller voltage steps: –reduce the step amplitude on the instrument –use attenuators Note: always utilizes the initialization procedure to set 0  reference level. It is also suggested to store the waveforms in open or short conditions to use as reference level.

49. TDR Applications TL & cable loss TL discontinuities (vias, bend) RLC parasitic measurements Packages Connectors impedance & crosstalk Common mode filters parasitic Dynamic impedance at inputs/outputs Dynamic impedance at clamping diodes

50. Coaxial Cable Modeling Bcable 1 0 2 0 + S11=PWL(0ns -30m 20.4ns 0m 20.6ns 30m 22n 22m 28n 18m 45n 9m 100n 2m) Z0=50 TD=0 + S21=PWL(0ns 0 100ps 0.1 300ps 0.8 1ns.93 3ns.96 8ns.99 18ns 0.998) Z0=50 TD=10.2ns S 21 S 11 DUT TDR 1 2 S 11= S 22 S 21= S 12

51. Balanced Interconnection TDR Modeling Balanced cables (two conductors + reference) Balanced transmission lines (two lines + reference plane) 4 measures: Common mode TDR/TDT Differential mode TDR/TDT Symmetrical geometry Asymmetrical geometry Full 4-port characterization: max 16 S-parameters

52. Balanced Interconnection Model For symmetrical structures it is possible to define: Z even : impedance of single conductor versus the ground Z odd : impedance of single conductor versus the symmetry plane of the two conductors There is a Sprint primitive (bimodal adapter) that can be used to create models based on two TL with Zeven and Zodd impedance Zeven, TD Zodd, TD Bimodal adapter

53. Common Mode Impedance TDR 50ohm 1 -0.3  -0.6  00 0.3  0.6  1 com 3 Z even =2*Z common Zcommon = 47.1ohm From a theoretical point of view it is possible to measure the Common Mode impedance: ground Example of crossection And then evaluate the Zeven: 300um 35um 150um 35um 200um Er=4.5

54. Common Mode Impedance Both TDR steps are positive TDR steps must be aligned during setup DUT must be connected to TDR through two cables of the same length  TDR 50ohm 1 2 5pF 3 4 S11 even =(S11 1com + S11 2com ) / 2 at 50ohm reference impedance From a practical point of view the measure is done using two TDR heads: S21 even =(S21 3com + S21 4com ) / 2 at 50ohm reference impedance 0.25  0.0  0.5  11 S11 1com S11 2com S21 3com S21 4com Start PWL End PWL

55. Differential mode Impedance TDR steps must have opposite direction TDR steps must be aligned during setup DUT must be connected to TDR through two cables of the same length TDR 50ohm 1 2 5pF 3 4 S11 odd =(S11 1dif - S11 2dif ) / 2 at 50ohm reference impedance S21 odd =(S21 3dif - S21 4dif ) / 2 at 50ohm reference impedance -0.5  -1.0  00 0.5  1.0  S11 1dif S11 2dif S21 4dif S21 3dif Start PWL End PWL

56. Balanced Interconnection Model S11even,S21even S11odd,S21odd Bimodal adapter AM2 Bimodal adapter AM1.SUBCKT BALANCED_LINE 100 200 1000 2000 AM1 100 200 1 2 BCOM 1 0 10 0 S11=PWL (0.00ns -0.005V 0.25ns 0.31V 6.57ns 0.305V 6.63ns 0.03V + 12.82ns 0.03V 13.14ns -0.005V 18.88ns 0.00V) Z0=50 TD=0 + S21=PWL(0 0 100p 1) Z0=50 TD=1.6N BDIFF 2 0 20 0 S11=PWL (0.00ns +0.005V 0.19ns -0.19V 3.22ns -0.19V 3.41ns -0.835V + 3.66ns -0.305V 3.92ns -0.22V 4.29ns -0.185V 6.51ns -0.195V + 6.57ns -0.085V 6.76ns -0.135V 7.20ns -0.03V 8.02ns -0.00V + 9.60ns -0.005V 10.23ns -0.035V 11.12ns -0.00V 18.82ns -0.00V) Z0=50 TD=0 + S21=PWL(0 0 100p 1) Z0=50 TD=1.6N AM2 1000 2000 10 20.ENDS BALANCED_LINE.SUBCKT BALANCED_LINE 100 200 1000 2000 or its TL equivalent AM1 100 200 1 2 (without capacitor only )TLCOM 1 10 Z0=94.5 TD=1.6N TLDIFF 2 20 Z0=34.0 TD=1.6N AM2 1000 2000 10 20.ENDS BALANCED_LINE 100 200 1000 2000 1 2 10 20 The model validation is done by simulating the TDR measurement setup.

57. Changing Reference Impedance in S-params 0.0  0.5  11 S11a S21a 11 0.0  0.5  S11b S21b TDR/TDT responses of lossy TL (Z0=90ohm) measured with a 50ohm TDR S11a,S21a 90ohm TDR 90ohm S21b S11b The model is simulated with a TDR configuration having 90ohm reference impedance B50ohm 1 0 2 0 S11=PWL( ) Z0=50 TD=0 + S21=PWL( ) Z0=50 TD=delay B90ohm 1 0 2 0 S11=PWL( ) Z0=90 TD=0 + S21=PWL( ) Z0=90 TD=delay A new model is obtained at 90ohm reference impedance

58. R, L, C with parasitic lumped equivalent circuits TDR models Common mode filters lumped equivalent circuits TDR models “Pure” TDR models can be developed for components with a maximum of four ports under the hypothesis of linear devices. Non linear devices must be modeled through mixed models. Note: a common mode choke can be modeled under the hypothesis of constant inductive behavior (no saturation effects) RLC parasitic

59. Ground plane Ground pin connection 50ohm semi-rigid coaxial cable (to TDR) DUT connection Cable shield connection to ground plane t +1 rho -1 rho t +1 rho -1 rho t +1 rho -1 rho The TDR characterization is performed with one of the two pins connected to ground. The model obtained can be used “as it is” for component utilized in the same configuration. For “series” connections, a “serial adapter” must be used (see SPRINT user’s manual) R L C TDR on 2-pin R, L and C

60. TDR: TL discontinuities

61. IC Packages and input capacitance measurement setup Ground plane Ground pin connection 50ohm semi-rigid coaxial cable (to TDR) Power rail SMD capacitor Power pin connection DUT connection Cable shield connection to ground plane To power supply

62. IC Package response 0 +1 Rho ceramic plastic

63. IC Package BTM models 0 +1 Rho BTM block Integrated model Divided model

64. IC Package Integrated model Two ways to describe the scattering parameter: by file by PWL (Piece-Wise Linear approximation) By file: 1) store a.g file of the measure 2) complete the file with Z0 and TD parameters 3) create a Bxxxx statement Bin 1 0 S11=FILE(filename) By PWL: 1) capture the measure in Sights 2) activate the command PWL extract 3) save the PWL approximation on file 4) create a Bxxxx statement by including the PWL approximation Bin 1 0 S11=PWL(0n 0 100ps 0.1 200ps 0.1 250ps -.05 400ps.4 800ps.9 1.2ns 1) Z0=50 TD=0

65. IC Package PWL approximation 0 +1 Rho

66. A 50ohm DC-block capacitor is added to protect the TDR heads. The bias current/voltage must be applied through high impedance paths (Z bias ): –High value resistor (> 2K) for voltage biasing –Inductance for current biasing (5-10uH) DUT 50ohm resistor Vtdr Cdc Z0=50 Td=1ns Zbias Vbias Power & Ground and other biasing 1 Biased TDR measurements NOTE: If case of inductive Zbias, the TDR MUST be disconnected before changing the biasing current value.

67. DC block Capacitor The DC block capacitor introduces a constant time that must be taken into account measuring low impedance. V t(  s) V t( n s) V t(  s) V t( n s) V t(  s) V t( n s) 1V (50ohm) 0.16V (10ohm) error 1V (50ohm) 0.16V (10ohm) error 1V (50ohm) 0.16V (10ohm) R=50ohm Vtdr 20 nF Z0=50ohm R=10ohm L=5nH V R=50ohm Vtdr Z0=50ohm R=10ohm L=5nH V R=50ohm Vtdr 2 nF Z0=50ohm R=10ohm L=5nH V

68. Inductive Zbias The biasing inductance introduces a constant time that must be taken into account measuring high impedance. V t(  s) V t( n s) V t(  s) V t( n s) V t(  s) V t( n s) 1V (50ohm) error 1V (50ohm) error 1V (50ohm) R=50ohm Vtdr Z0=50ohm C=20p V R=50ohm Vtdr Z0=50ohm C=20p V R=50ohm Vtdr Z0=50ohm C=20p V error Z= 25  H Z= 5  H

69. Biasing set-up The interconnection between the biasing resistor or inductance must be as short as possible. Biasing position: - close to DUT - far from DUT R=50ohm Vtdr Z0=50ohm Zbias R=50ohm Vtdr Z0=50ohm Zbias DUT  ttt   t  B A A C D A line

70. Receiver Static Characteristics (IBIS, THRIS) Input capacitance (IBIS, THRIS) Dynamic behaviours (THRIS only) Drivers Static Characteristics (IBIS, THRIS) Output capacitance (IBIS, THRIS) Unloaded output waveform (IBIS, THRIS) Dynamic behaviours (THRIS only) Macromodels can be extracted by simulating the Spice models (if available) of single I/O cells. The simulation configuration is quite similar to the measurement setup. Modeling from Spice

71. Receiver Static Characteristics 1) Connect the power/ground pins of the Spice model to power supply and sets up the other biasing pins (if available) 2) Connect a DC voltage supply to the input pin of the Spice model through a sensing resistor of very low value (~0ohm) 3) Run a DC analysis sweeping the DC voltage supply with the following ranges: IBIS 2.1: -VCC up to 2VCC (required) Step suggested=50mV THRIS: GND-2V up to VCC+2V (suggested) Step suggested=50mV 4) Store the voltage on the input pin of Spice model and the current in the sensing resistor DUT 0ohm resistor DC Power & Ground and other biasing

72. Modeling from Spice Receiver TDR simulation STEP 1: a) Connect the power/ground pins of the Spice model to power supply and sets up the other biasing pins (if available) b) Connect input biasing voltage or current supply to the input pin of the Spice model through an impedance Zbias c) Run a DC analysis d) Read the steady state voltage at the node 1 (Vsteady) STEP 2: e) Connect a step voltage generator with a 50 ohm internal resistor to node 1 through a 50 ohm impedance transmission line (TD=1ns suggested) f) Set Vtdr with the correct voltage step taking Vsteady into account g) Store the transient analysis at node 2 DUT 50ohm resistor Vtdr Z0=50 Td=1ns Zbias Vbias/Ibias Power & Ground and other biasing 1 2 Second step

73. Modeling from Spice Receiver TDR simulation: step 1 DUT 50ohm resistor Vtdr Z0=50 Td=1ns Zbias Vbias/Ibias Power & Ground and other biasing 2 The TDR response depends on the operating point. The bias generator could be: voltage biasing (high impedance inputs) through a voltage power supplier –CMOS/TTL/ECL: normal operating voltage (0-5V, 0-3.3V, etc.) Zbias= 10k resistor typ current biasing (low impedance inputs) through a current supply generator –CMOS/TTL/ECL clamping conditions voltage ( Vcc ) –receiver with internal termination Zbias = 0ohm resistor The transient analysis must be sufficiently long to evaluate the steady state voltage at point 1 (Vsteady) 1

74. Modeling from Spice Receiver TDR simulation: step 2 DUT 50ohm resistor Vtdr Z0=50 Td=1ns Zbias Vbias/Ibias Power & Ground and other biasing 2 The TDR voltage starts from Vsteady value. The amplitude of the step should be small in order to reduce the risk of operating point modifications in the device under test. Typical value of Vtdr step is 50mV. The rise time of Vtdr could be of the order of 20-30ps. The transient analysis must store the voltage at point 2. The last section of the transient analysis represents the TDR response where Vsteady level correspond to -1 RHO and Vsteady+50mV correspond to +1 RHO. 1 t Vtdr Vsteady Vsteady+50mV 10ns 20ps t V2 Vsteady Vsteady+50mV +1 RHO -1 RHO 0 RHO High impedance Low impedance

75. Clamping diode charact.

76. Modeling from Spice 1) Connect the power/ground pins of the Spice model to power supply and sets up the other biasing pins (if available) 2) Connect a DC voltage supply to the input pin of the Spice model and use it to set the output pin of the driver at “0” or “1” logic level (2 simulations) 3) Connect a DC voltage supply to the output pin of the Spice model through a sensing resistor of very low value (~0ohm) 4) Run a DC analysis sweeping the DC voltage supply according with the following ranges: “0” logic: IBIS 2.1: -VCC up to 2VCC (suggested) Step suggested=50mV THRIS: GND-2V up to VCC (suggested) Step suggested=50mV “1” logic: IBIS 2.1: -VCC up to 2VCC (suggested) Step suggested=50mV THRIS: GND up to VCC+2V (suggested) Step suggested=50mV 5) Store the voltage on the output pin of Spice model and the current in the sensing resistor Static Output Characteristics DUT 0ohm resistor DC Power & Ground and other biasing “0” or “1” logical level

77. Modeling from Spice 1) Connect the power/ground pins of the Spice model to power supplies and sets up the other biasing pins (if available) 2) Connect a PULSE voltage supply to the input pin of the Spice model. 3) Run a TRANSIENT analysis. 4) Store the voltage at the output pin of Spice model. DUT 0ohm resistor DC Power & Ground and other biasing “0” or “1” logical level Unloaded Output Waveform

78. Modeling from Spice Driver TDR simulation STEP 1: a) Connect the power/ground pins of the Spice model to power supplies and sets up the other biasing pins (if any). b) Connect a DC voltage supply to the input pin of the Spice model and use it to set the output pin of the driver at “0” or “1” logic level b) Connect input biasing voltage or current supply to the input pin of the Spice model through an impedance Zbias c) Run a DC analysis and read the steady state voltage at the node 1 (Vsteady) STEP 2: e) Connect a step voltage generator with a 50 ohm internal resistor to node 1 through a 50 ohm impedance transmission line (TD=1ns suggested) f) Set Vtdr with the correct voltage step taking Vsteady into account g) Store the transient analysis at node 2 DUT 50ohm resistor Vtdr Z0=50 Td=1ns Zbias Vbias/Ibias Power & Ground and other biasing 1 2 Second step “0” or “1” logical level

79. Modeling from Spice Driver TDR simulation: step 1 DUT 50ohm resistor Vtdr Z0=50 Td=1ns Zbias Vbias/Ibias Power & Ground and other biasing 2 The operating point influences the TDR response. The bias generator is usually of type “current”: Current biasing (outputs are at low impedance) through a current supply generator –CMOS/TTL/ECL normal and clamping conditions voltage : Vcc clamp (4 regions for accurate models). Zbias = 0 ohm resistor The transient analysis must be sufficiently long to evaluate the steady state voltage at point 1 (Vsteady) 1

80. Modeling from Spice Driver TDR simulation: step 2 DUT 50ohm resistor Vtdr Z0=50 Td=1ns Zbias Vbias/Ibias Power & Ground and other biasing 2 The TDR voltage starts from Vsteady value. The amplitude of the step should be small in order to reduce the risk of operating point modifications in the device under test. Typical value of Vtdr step is 50mV. The rise time of Vtdr could be of the order of 20-30ps. The transient analysis must store the voltage at point 2. The last section of the transient analysis represents the TDR response where Vsteady level correspond to -1 RHO and Vsteady+50mV correspond to +1 RHO. 1 t Vtdr Vsteady Vsteady+50mV 10ns 20ps t V2 Vsteady Vsteady+50mV +1 RHO -1 RHO 0 RHO High impedance Low impedance

81. Example of output TDR char

82. Connector models LC –3D L,C descriptions with mutual inductors S-parameter –single pin: 2-port scattering parameters discontinuity –two pins: 4-port scattering parameters discontinuity crosstalk TL –n-pins: based on unbalanced and balanced TL discontinuity crosstalk TL based models require recursive model optimization

83. TDR Analysis on Connector The TDR is connected to one of the pin (pin under test) All pins surrounding the TDR injection point are connected to 50ohm terminations (reference impedance) TDR and TDT are measured for the pin under test Near-end and Far-end crosstalk is measured for the surrounding pins Only the crosstalk between adjacent pins is taken into account

84. Measurement configurations The characterization must be repeted for all different pin configurations. For example, for a regular pin matrix (homogeneous density in row and column directions): 50ohm termination TDR head DSO (near-end crosstalk) unconnected pins TDR on central pin Xtalk on nearest pin TDR on central pin Xtalk on diagonal pin TDR on lateral pin Xtalk on nearest pin TDR on lateral pin Xtalk on diagonal pin TDR on corner pin Xtalk on nearest pin TDR on corner pin Xtalk on diagonal pin Note: the connections on the other side of the connector are not reported in the figure 1 2 3 4 5 6

85. Connector TDR measurement setup A common ground reference plane must be defined around connector pins TDR/TDT connections with 50 cable 50 ohm termination for surrounding pins As short as possible connections connector Copper foil (GND)

86. Connector Lattice Model

88. Input Capacitance

90. Extracting pure dynamic behavior = Active device Package t Active device Package t Active device Package t Active device Package t + + V I S11,S22, S21 S11 Package is extracted and modeled as a 2- port S-param element The dynamic behavior of the non linear resistance is ideal V/I charact. “pure” dynamic behavior of the active circuitery

94. SPRINT simulator Spice-like syntax DSP based

95. Primitives Linear R,L,C Non linear resistors Time controlled resistor Voltage controlled resistors Independent sources Voltage/current controlled sources Time-domain scattering parameters...

96. Resistors, Capacitors and Inductors Resistor: an active power load (positive sign) or generator (negative sign) Inductor: a reactive power “storage” Capacitor: a reactive power storage

97. Non-Linear Resistors Linear resistor V I V/I = R (constant) Non-linear resistor V I V/I = V I v1 i1 v2 i2 v3 i3 …... Non-linear resistors can show a non-monotone shape and a no-crossing zero behaviour Non-linear resistors are widely used to describe clamping diode or driver’s pull-up/pull-down transistors Pxxxx 1 2 -5V -10mA -3V -1mA -0.5V -0.1mA 0V 0A 1V 10mA 2V 100mA Z0=value C= value L=value

98. Mutual Inductors

99. Controlled Voltage/Currents Sources (1) Example 1: simple 5V voltage source controlled by a 3.3V input ( with linear 30ohm output impedance ) Vxxxx 20 0 10 0 s(t)=PWL(0 0 1ns 1v 1.5ns 1.2v 2ns.9v 3ns 1) THR(1.5 0 5) 3N 30 The control chain must be applied starting from the end: 1) Delay, 2) static transfer function, 3) dynamic transfer function in this case: Vout Vin t s(t) 1 3N Vth DELAY Static Transfer Function Dynamic Transfer Function t Vin 3.3 t Vin 3.3 3n t 5 t 5

100. Controlled Voltage/Currents Sources(2) Static and dynamic characteristics order is very important: a complete different result is obtained if the order is reversed: Vxxxx 10 0 20 0 THR(1.5 0 5) s(t)=PWL(0 0 1ns 1v 1.5ns 1.2v 2ns.9v 3ns 1) 3N 30 The control chain must be applied starting from the end: 1) Delay, 2) dynamic transfer function, 3) static transfer function in this case: 3N Vout Vin Vth DELAY Static Transfer Function t s(t) 1 Dynamic Transfer Function t Vin 3.3 t Vin 3.3 3n t 3.3 3n t 5

101. Controlled Voltage/Currents Sources(3) Application: Starting from a “0-1 logic level” bit sequence create a “5V” signal with a jitter that is a function of the intersymbol interference Vstim 1 0 PULSE(0 1 0 100P 100P 10N 10N) PSEQ(01001011101000001001111101110001100111111011110011000010010) Einterference 2 0 1 0 THR(0.5 0 1) s(t)=PWL(0 0 1N 0.4.4 10N 0.8 25N 0.95 60N 1) Eout 3 0 2 0 s(t)=PWL(0 0 0.4N 0.15 1.5N 0.9 2N 1.2 2.5N 1.3 3N 0.8 4N 1.1 5N 1) 5 Rout 3 4 20 Cout 4 0 10P Node 1 (input pattern) Node 4 (output pattern)

102. Voltage/Current Controlled Resistors(1).SUBCKT LV_DR4_4 1 2 10 20 * in out VCC GND * output capacitance Cout2 0 7pf * pull-up Rsw1 7 2 1 0 PWL(0V 1e6.2 10K.3 2K.4 1K 0.5V 300.6 250.7 150.8 100.9 40 1V.1 2V.1 ) Pvcc 7 10 -3.3V -25mA -2V -23mA -1V -18mA 0 0 1V 0 C=.2P * pull-down Rsw2 17 2 1 0 PWL(-1V.1 0V.1.1 40.2 100.3 150.4 250.5V 300.6 1K.7 3K.8 10K 1V 1e6) Pgnd 17 20 -1V 0 0V 0 1V 18mA 2V 23mA 3.3V 25mA.ENDS LV_DR4_4 in out vcc gnd out (2) vcc (10) gnd (20) in (1) out (2) Cout Pvcc Pgnd Rsw1 Rsw2

103. Voltage/Current Controlled Resistors(2) Vgs Vds Ids Vds Ids B2 B3 B1 C A Vgs=5V Vgs=4V Vgs=3V Vgs=2V 1 2 3 4 t Vds 3 2 1 A C C C B Rise times of Vgs Vds Ids C A Vgs=5V Vgs=4V Vgs=3V Vgs=2V 1 2 3 4 t Vds 1 2 3 A C C C B Rise time of Vgs B3 B2 B1

104. Voltage/Current Controlled Resistors(3) Rsw1 Rsw2 Gnd Vcc Moving up and down the characteristics modify the unloaded output rise/fall times The PWL shapes modify the trajectories on the V/I output graph The speed (and shape) of the Vgs transitions have influence on the unloaded output rise/fall times Vgs The central section of the characteristics influences the feed-through current