1. Technology Evolution

2. Digital signal Problems Single net Multiple net Reflection EMC radiation Stub ringing Jitter Losses Crosstalk SSN Power supply distribution noise Clock tree skew EMC radiation

3. Rise/Fall times (T r,T f ) Multi-crossing threshold High level overshoot (V ov ) Low level oveshoot Ringing Static levels Level references (V ih, Vil) Waveform Parameters

4. When to Worry About SI T r > T pd Multi-pin connectors Wide buses Heavily loaded lines Loads concentrated Buses cannot be terminated New, unproven devices Critical timing

5. Analysis Tool Be careful : you can spend 2 days or 2 months for the analysis Analyze and understand criteria and analysis tools Identify the potential problem areas Measure new phenomena / technologies (Oscilloscope, TDR, Network analyzer) Domains: Time domain and Frequency Domain

6. This definition apply at any interconnection level: Within chips (Leadframes) Between components (PCB traces) Between boards (Connectors) Between subsystems (Cables) Transmission Line

7. Resistance per Unit Length Inductance per Unit Length Capacitance per Unit Length Conductance per Unit Length Lossless case: R = 0, G = 0 Transmission Line

8. Physical description thickness width length crossection Electrical characteristics Z0 (impedance) Tpd (delay) loss

9. Transmission Line Characteristics

10. Voltage and Current Waves V(x,t) = Vi + Vr I(x,t) = Ii + Ir 1) For the first waveform, the transmission line shows its line impedance 2) The incident wave travels down the line. After Tpd time, the waveform hits the load, and a portion of the wave is reflected. 3) The reflected wave travels down the line. After Tpd time, the waveform hits the source, and a portion of the wave is reflected.

11. Definition: Special cases: when Z = Z0 (matched impedance) when Z = infinite (open circuit) when Z = 0 (short circuit ) Reflection Coefficient

12. normalembedded Conductor dielectric reference plane Disadvantages: nonhomogeneous medium (far- end crosstalk) Potential EMC problems Advantages: Faster than strip-lines Good for higher impedance Propagation speed is reduced of a factor Microstrips (normal and embedded)

13. normal Disadvantages: Slower than microstrip Advantages: Homogeneous medium (no far- end crosstalk) Reduced EMC problems Good for lower impedance Good for balanced signals (dual offset) dual offset Propagation speed is reduced of Striplines

14. Crosstalk is coupling of unwanted energy (signal) onto a victim line Coupling among TL (coupled lines in PCBs/leadframes/cables) Impedance of common current returns paths (Ground bounce) Coupling in connectors Indirect electromagnetic coupling (EMC) In this document crosstalk will refer to the direct coupling mechanism only (coupled lines in PCB/leadframe/cables and connectors) For each signal there is a “noise budged” allowed. All previous phenomena contribute to this budged What-is Crosstalk

15. Clock signals Long address / data buses Analog signals in digital circuits Asynchronous Signals (reset, etc) The configurations could be very complex where more signals can contribute to total crosstalk noise. For example: Ground signal Analog signal (victim) Clock signal (aggressor) Reset signal (victim) Read/Write signal (aggressor) Data signal(aggressor) Sensitive Signal Lines

16. A single line presents a very simple electromagnetic field configuration In general: a multi-conductor system of n conductors (excluding the reference conductor) shows n propagation modes. Two coupled lines show a more complex electromagnetic field configuration. There are two propagation modes and two propagation speeds. Electrical (green) and magnetic (blue) fields Electrical fields for even (left) and odd (right) for conductor A (magnetic field is omitted for simplicity) A B Parallel Trace Crosstalk

17. I c - I l RtRt cmcm lmlm RtRt RtRt RtRt x I c + I l Far-end crosstalk Near-end crosstalk ToTo 2T o T r +2 T TrTr T r + T reflection Case study: two-line symmetrical: two propagation MODEs (odd and even) homogeneous material -> Far-end crosstalk = 0 R t = termination resistor T r = rise time of the incident wave T o = propagation delay of the odd mode T e = propagation delay of the even mode T = difference between even and odd propagation delays Note: R t is calculated in order to match the impedance of the coupled structure to reduce reflections B A CD A B C D

18. Far-End Crosstalk RtRt cmcm lmlm RtRt RtRt RtRt x B A CD Far-end crosstalk ToTo TrTr T r + T A B C D The amplitude is a function of the coupling coefficient, but could be is “clamped” if the rise time is larger than the difference between the propagation delays of the two modes. At least, the amplitude can be 0 if the two modes propagates at same speed (case homogeneous material) Far-end crosstalk between two lines with an input signal of 200ps versus  T  T=0p Rise time=200p  T=50p  T=100p  T=150p  T=200p  T=250p  T=300p

19. RtRt cmcm lmlm RtRt RtRt RtRt x B A CD Near-end crosstalk 2T o T r +2 T TrTr A B C D Amplitude is only a function of the coupling coefficient. Near-end crosstalk between two lines with an input signal of 200ps versus  T (50ps step) TT 0 300ps Near-End Crosstalk

20. Incident and Transmitted Pulses RtRt cmcm lmlm RtRt RtRt RtRt x B A CD TrTr A B C D The transmitted pulse shows first an amplitude reduction due to loss of energy coupled to line CD. The incident waveform shows some reflections of the far-end crosstalk due to the different velocity of the propagation modes Reflection

21. When the total length of the interconnection is long enough to be transmissive. With the actual technologies, length could be very short LS70 cm A, ALS25 cm FAST, FACT, ACT, AC, AS, BCT, LV15 cm ECLinPS3 cm When Use Termination

22. Matched Termination is possible if: Single path, no branches, no loads (Not practical) Matched source Matched load Reflections are eliminated at the far end of the signal paths BUT: Signal level is cut down by half (only point to point) High driver/return current and power dissipation Matched Termination

23. The effective line impedance is defined by a combination of: The unloaded line impedance The effect of stubs (Zeff decrease) The effect of loads (Zeff decrease), usually capacitive. Starting from a unloaded line of about 100 ohms it is normal to obtain an effective impedance of 25-60ohm Effective Line Impedance

24. Eye diagrams are obtained by superimposing all the time frames of a bit-sequence. This function is very useful to check the quality of a data transmission channel. Usually, this function requires the definition of stimulus signals with long bit-sequences Eye openingJitter Eye-diagram

25. Data detection is synchronized by the clock signal, that defines the bit-width. clock data Bit width Eye-diagram

26. Consider a waveform at receiver for a single edge signal Z0, Td t setup Inter-symbol interference occurs when: bit_width < t setup t setup is the settling time required to extinguish the transient. Example: settling time t setup = 11 ns 1) 200Mb/s bit-rate 5ns bit-width 3 bits (11/5) of inter-symbol interference 2) 500mb/s bit-rate 2ns bit-width 6 bits (11/2) of inter-symbol interference Note: previous bits could be 0 or 1. There are a lot of possible combinations pseudo-random bit sequences Inter-symbol interference

27. Eye-diagrams examples (1) This eye-diagram shows a bounce in the middle of the bit-time due to a mismatch of impedance that produce a noise margin reduction on signal levels in a critical point. The rise waveform shows a sliced edge due to the inter- symbolic interference This eye-diagram shows a strong jitter mainly due to the asymmetry between the “1” logic and the “0” logic bit widths

28. Eye-diagrams examples (2) Both eye-diagrams show a defect due to the rise and fall edges. The one on left shows a slow edge compared to the data transmission speed and the one on the rights shows non-monotone rising/falling edges.

29. Eye-diagram measurements are performed by oscilloscopes. Data Trigger in in DSO Signal under test Clock signal Common functions available on DSO: persistence jitter statistical distribution Bit-sequence: the actual bit-sequence of the system (in laboratory: a pseudo-random bit-sequence) Measuring Eye-diagrams

30. Simulated eye-diagram are obtained starting from simulations with long bit-sequences But: Which sequence? (PRBS, exhaustive?) How many bits generate significant inter-symbol interference? (strong impact on simulation time) Long simulation time Example: if the interconnection causes significant inter-symbol interference for 6 bits, an exhaustive analysis requires a bit-sequence containing 2 6 combinations (000000, 000001, 000010, …, 111111). The total sequence will be 64 x 6 = 384 bits long. If each bit is 10ns (100Mbit/s), the total simulation time will be about 4us. Simulating Eye-diagrams

32. TDR/TDT Basics TDR: Time Domain Reflectometry TDT: Time Domain Transmission –A voltage step is propagated down the transmission line under investigation, and the incident and reflected voltage waves are monitored by the oscilloscope at a particular point on the line Step-wave generator Oscilloscope DUT Launch cable (Z0) TDT TDR

33. TDR: Resolution two discontinuities become indistinguishable when separated by a time (and related distance) that is less than half of the risetime Example of two discontinuities 2mm apart. They can be distinguished only with a 10ps risetime

34. Multiple discontinuities  1 % error in  2 0.01 <.25%.05 ~ 2%.10 ~ 6% The first discontinuity has a maximum reflection coefficient of  1 and the second of  2. The table shows that the percent error in  2 due to  1 could be very high also for small value of  1. The first discontinuity causes a degradation of rise time and loss of accuracy on the second discontinuity

35. Normalization

36. TDR Amplitude Normally 250-400mV Some characterizations require smaller voltage steps: –reduce the step amplitude on the instrument –use attenuators Note: always utilizes the initialization procedure to set 0  reference level. It is also suggested to store the waveforms in open or short conditions to use as reference level.

37. TDR Applications TL & cable loss TL discontinuities (vias, bend) RLC parasitic measurements Packages Connectors impedance & crosstalk Common mode filters parasitic Dynamic impedance at inputs/outputs Dynamic impedance at clamping diodes

38. Coaxial Cable Modeling Bcable 1 0 2 0 + S11=PWL(0ns -30m 20.4ns 0m 20.6ns 30m 22n 22m 28n 18m 45n 9m 100n 2m) Z0=50 TD=0 + S21=PWL(0ns 0 100ps 0.1 300ps 0.8 1ns.93 3ns.96 8ns.99 18ns 0.998) Z0=50 TD=10.2ns S 21 S 11 DUT TDR 1 2 S 11= S 22 S 21= S 12

39. Balanced Interconnection TDR Modeling Balanced cables (two conductors + reference) Balanced transmission lines (two lines + reference plane) 4 measures: Common mode TDR/TDT Differential mode TDR/TDT Symmetrical geometry Asymmetrical geometry Full 4-port characterization: max 16 S-parameters

40. Balanced Interconnection Model For symmetrical structures it is possible to define: Z even : impedance of single conductor versus the ground Z odd : impedance of single conductor versus the symmetry plane of the two conductors There is a Sprint primitive (bimodal adapter) that can be used to create models based on two TL with Zeven and Zodd impedance Zeven, TD Zodd, TD Bimodal adapter

41. Common Mode Impedance TDR 50ohm 1 -0.3  -0.6  00 0.3  0.6  1 com 3 Z even =2*Z common Zcommon = 47.1ohm From a theoretical point of view it is possible to measure the Common Mode impedance: ground Example of crossection And then evaluate the Zeven: 300um 35um 150um 35um 200um Er=4.5

42. Common Mode Impedance Both TDR steps are positive TDR steps must be aligned during setup DUT must be connected to TDR through two cables of the same length  TDR 50ohm 1 2 5pF 3 4 S11 even =(S11 1com + S11 2com ) / 2 at 50ohm reference impedance From a practical point of view the measure is done using two TDR heads: S21 even =(S21 3com + S21 4com ) / 2 at 50ohm reference impedance 0.25  0.0  0.5  11 S11 1com S11 2com S21 3com S21 4com Start PWL End PWL

43. Differential mode Impedance TDR steps must have opposite direction TDR steps must be aligned during setup DUT must be connected to TDR through two cables of the same length TDR 50ohm 1 2 5pF 3 4 S11 odd =(S11 1dif - S11 2dif ) / 2 at 50ohm reference impedance S21 odd =(S21 3dif - S21 4dif ) / 2 at 50ohm reference impedance -0.5  -1.0  00 0.5  1.0  S11 1dif S11 2dif S21 4dif S21 3dif Start PWL End PWL

44. Balanced Interconnection Model S11even,S21even S11odd,S21odd Bimodal adapter AM2 Bimodal adapter AM1.SUBCKT BALANCED_LINE 100 200 1000 2000 AM1 100 200 1 2 BCOM 1 0 10 0 S11=PWL (0.00ns -0.005V 0.25ns 0.31V 6.57ns 0.305V 6.63ns 0.03V + 12.82ns 0.03V 13.14ns -0.005V 18.88ns 0.00V) Z0=50 TD=0 + S21=PWL(0 0 100p 1) Z0=50 TD=1.6N BDIFF 2 0 20 0 S11=PWL (0.00ns +0.005V 0.19ns -0.19V 3.22ns -0.19V 3.41ns -0.835V + 3.66ns -0.305V 3.92ns -0.22V 4.29ns -0.185V 6.51ns -0.195V + 6.57ns -0.085V 6.76ns -0.135V 7.20ns -0.03V 8.02ns -0.00V + 9.60ns -0.005V 10.23ns -0.035V 11.12ns -0.00V 18.82ns -0.00V) Z0=50 TD=0 + S21=PWL(0 0 100p 1) Z0=50 TD=1.6N AM2 1000 2000 10 20.ENDS BALANCED_LINE.SUBCKT BALANCED_LINE 100 200 1000 2000 or its TL equivalent AM1 100 200 1 2 (without capacitor only )TLCOM 1 10 Z0=94.5 TD=1.6N TLDIFF 2 20 Z0=34.0 TD=1.6N AM2 1000 2000 10 20.ENDS BALANCED_LINE 100 200 1000 2000 1 2 10 20 The model validation is done by simulating the TDR measurement setup.

45. Changing Reference Impedance in S-params 0.0  0.5  11 S11a S21a 11 0.0  0.5  S11b S21b TDR/TDT responses of lossy TL (Z0=90ohm) measured with a 50ohm TDR S11a,S21a 90ohm TDR 90ohm S21b S11b The model is simulated with a TDR configuration having 90ohm reference impedance B50ohm 1 0 2 0 S11=PWL( ) Z0=50 TD=0 + S21=PWL( ) Z0=50 TD=delay B90ohm 1 0 2 0 S11=PWL( ) Z0=90 TD=0 + S21=PWL( ) Z0=90 TD=delay A new model is obtained at 90ohm reference impedance

46. R, L, C with parasitic lumped equivalent circuits TDR models Common mode filters lumped equivalent circuits TDR models “Pure” TDR models can be developed for components with a maximum of four ports under the hypothesis of linear devices. Non linear devices must be modeled through mixed models. Note: a common mode choke can be modeled under the hypothesis of constant inductive behavior (no saturation effects) RLC parasitic

47. Ground plane Ground pin connection 50ohm semi-rigid coaxial cable (to TDR) DUT connection Cable shield connection to ground plane t +1 rho -1 rho t +1 rho -1 rho t +1 rho -1 rho The TDR characterization is performed with one of the two pins connected to ground. The model obtained can be used “as it is” for component utilized in the same configuration. For “series” connections, a “serial adapter” must be used (see SPRINT user’s manual) R L C TDR on 2-pin R, L and C

48. IC Packages and input capacitance measurement setup Ground plane Ground pin connection 50ohm semi-rigid coaxial cable (to TDR) Power rail SMD capacitor Power pin connection DUT connection Cable shield connection to ground plane To power supply

49. IC Package response 0 +1 Rho ceramic plastic

50. IC Package BTM models 0 +1 Rho BTM block Integrated model Divided model

51. IC Package Integrated model Two ways to describe the scattering parameter: by file by PWL (Piece-Wise Linear approximation) By file: 1) store a.g file of the measure 2) complete the file with Z0 and TD parameters 3) create a Bxxxx statement Bin 1 0 S11=FILE(filename) By PWL: 1) capture the measure in Sights 2) activate the command PWL extract 3) save the PWL approximation on file 4) create a Bxxxx statement by including the PWL approximation Bin 1 0 S11=PWL(0n 0 100ps 0.1 200ps 0.1 250ps -.05 400ps.4 800ps.9 1.2ns 1) Z0=50 TD=0

52. IC Package PWL approximation 0 +1 Rho

53. Connector models LC –3D L,C descriptions with mutual inductors S-parameter –single pin: 2-port scattering parameters discontinuity –two pins: 4-port scattering parameters discontinuity crosstalk TL –n-pins: based on unbalanced and balanced TL discontinuity crosstalk TL based models require recursive model optimization

54. TDR Analysis on Connector The TDR is connected to one of the pin (pin under test) All pins surrounding the TDR injection point are connected to 50ohm terminations (reference impedance) TDR and TDT are measured for the pin under test Near-end and Far-end crosstalk is measured for the surrounding pins Only the crosstalk between adjacent pins is taken into account

55. Measurement configurations The characterization must be repeted for all different pin configurations. For example, for a regular pin matrix (homogeneous density in row and column directions): 50ohm termination TDR head DSO (near-end crosstalk) unconnected pins TDR on central pin Xtalk on nearest pin TDR on central pin Xtalk on diagonal pin TDR on lateral pin Xtalk on nearest pin TDR on lateral pin Xtalk on diagonal pin TDR on corner pin Xtalk on nearest pin TDR on corner pin Xtalk on diagonal pin Note: the connections on the other side of the connector are not reported in the figure 1 2 3 4 5 6

56. Connector TDR measurement setup A common ground reference plane must be defined around connector pins TDR/TDT connections with 50 cable 50 ohm termination for surrounding pins As short as possible connections connector Copper foil (GND)

57. SPRINT simulator Spice-like syntax DSP based Allows TDR* modeling Simulation time grows with complexity linearly** * Time Domain Reflectometry ** Spice-based simulators grows exponentially

58. Primitives Linear R,L,C Non linear resistors Time controlled resistor Voltage controlled resistors Independent sources Voltage/current controlled sources Time-domain scattering parameters...

59. Resistors, Capacitors and Inductors Resistor: an active power load (positive sign) or generator (negative sign) Inductor: a reactive power “storage” Capacitor: a reactive power storage

60. Non-Linear Resistors Linear resistor V I V/I = R (constant) Non-linear resistor V I V/I = V I v1 i1 v2 i2 v3 i3 …... Non-linear resistors can show a non-monotone shape and a no-crossing zero behaviour Non-linear resistors are widely used to describe clamping diode or driver’s pull-up/pull-down transistors Pxxxx 1 2 -5V -10mA -3V -1mA -0.5V -0.1mA 0V 0A 1V 10mA 2V 100mA Z0=value C= value L=value

61. Independent Sources Voltage sources (Thevenin) Current sources (Norton) v I N+ N- N+ N- R R User-defined voltage or current sources with a linear internal resistor The voltage/current values can be fixed or variable

62. Independent Sources: functions DC function Pulse function Sinusoidal function PWL* function File Function others …. * Piece-Wise Linear Fixed values (power supplies, voltage references) ttttt Ascii file Digital signals with linear rise/fall times Sinusoidal signals (fixed or variable frequency and amplitude) Digital signals with non-linear rise/fall times Arbitrary user-defined signals

63. Controlled Voltage/Currents Sources (1) Example 1: simple 5V voltage source controlled by a 3.3V input ( with linear 30ohm output impedance ) Exxxx 20 0 10 0 s(t)=PWL(0 0 1ns 1v 1.5ns 1.2v 2ns.9v 3ns 1) THR(1.5 0 5) 3N 30 The control chain must be applied starting from the end: 1) Delay, 2) static transfer function, 3) dynamic transfer function in this case: Vout Vin t s(t) 1 3N Vth DELAY Static Transfer Function Dynamic Transfer Function t Vin 3.3 t Vin 3.3 3n t 5 t 5

64. Controlled Voltage/Currents Sources(2) Static and dynamic characteristics order is very important: a complete different result is obtained if the order is reversed: Vxxxx 10 0 20 0 THR(1.5 0 5) s(t)=PWL(0 0 1ns 1v 1.5ns 1.2v 2ns.9v 3ns 1) 3N 30 The control chain must be applied starting from the end: 1) Delay, 2) dynamic transfer function, 3) static transfer function in this case: 3N Vout Vin Vth DELAY Static Transfer Function t s(t) 1 Dynamic Transfer Function t Vin 3.3 t Vin 3.3 3n t 3.3 3n t 5

65. Controlled Voltage/Currents Sources(3) Application: Starting from a “0-1 logic level” bit sequence create a “5V” signal with a jitter that is a function of the intersymbol interference Vstim 1 0 PULSE(0 1 0 100P 100P 10N 10N) PSEQ(01001011101000001001111101110001100111111011110011000010010) Einterference 2 0 1 0 THR(0.5 0 1) s(t)=PWL(0 0 1N 0.4.4 10N 0.8 25N 0.95 60N 1) Eout 3 0 2 0 s(t)=PWL(0 0 0.4N 0.15 1.5N 0.9 2N 1.2 2.5N 1.3 3N 0.8 4N 1.1 5N 1) 5 Rout 3 4 20 Cout 4 0 10P Node 1 (input pattern) Node 4 (output pattern)

66. Voltage/Current Controlled Resistors(1).SUBCKT LV_DR4_4 1 2 10 20 * in out VCC GND * output capacitance Cout2 0 7pf * pull-up Rsw1 7 2 1 0 PWL(0V 1e6.2 10K.3 2K.4 1K 0.5V 300.6 250.7 150.8 100.9 40 1V.1 2V.1 ) Pvcc 7 10 -3.3V -25mA -2V -23mA -1V -18mA 0 0 1V 0 C=.2P * pull-down Rsw2 17 2 1 0 PWL(-1V.1 0V.1.1 40.2 100.3 150.4 250.5V 300.6 1K.7 3K.8 10K 1V 1e6) Pgnd 17 20 -1V 0 0V 0 1V 18mA 2V 23mA 3.3V 25mA.ENDS LV_DR4_4 in out vcc gnd out (2) vcc (10) gnd (20) in (1) out (2) Cout Pvcc Pgnd Rsw1 Rsw2

67. Voltage/Current Controlled Resistors(2) Vgs Vds Ids Vds Ids B2 B3 B1 C A Vgs=5V Vgs=4V Vgs=3V Vgs=2V 1 2 3 4 t Vds 3 2 1 A C C C B Rise times of Vgs Vds Ids C A Vgs=5V Vgs=4V Vgs=3V Vgs=2V 1 2 3 4 t Vds 1 2 3 A C C C B Rise time of Vgs B3 B2 B1

68. Voltage/Current Controlled Resistors(3) Rsw1 Rsw2 Gnd Vcc Moving up and down the characteristics modify the unloaded output rise/fall times The PWL shapes modify the trajectories on the V/I output graph The speed (and shape) of the Vgs transitions have influence on the unloaded output rise/fall times Vgs The central section of the characteristics influences the feed-through current