1. Ground Planes

2. @ Copyright 1999 - F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyGP_2 Course outline Contents Digital Signal Model Non Ideal Behavior of Components High Speed Properties of Digital Gates Ground PlanesGround Planes Crosstalk Power Distribution Terminations Low frequency High frequency Current distribution Inductive crosstalk Slots in ground plane Additional inductance Two traces over a slot “Cross-finger” layout Advantages & disadvantages “Finger” layout Advantages & disadvantages Guard traces Use of guard traces Current paths Ground planes properties

3. @ Copyright 1999 - F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyGP_3 Low frequency In solid ground planes, at low frequencies, return currents follow path of least resistance (minimum distance) Signal trace Return path Ground plane

4. @ Copyright 1999 - F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyGP_4 High frequency In solid ground planes, at high frequencies, return currents follow a path of least inductance (minimum area) Signal trace Return path Ground plane

5. @ Copyright 1999 - F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyGP_5 Current distribution At high frequencies (typical digital circuits), return currents tend to stay near the signal trace, with a distribution in the cross-section given by: I 0 : total trace current 0 y w h Ground plane Signal current density

6. @ Copyright 1999 - F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyGP_6 Current distribution The current distribution in the cross-section influences other adjacent traces 0 y w h Ground plane  v I0I0 Inductive crosstalk Current distribution I(y) Magnetic flux  Induced voltage v

7. @ Copyright 1999 - F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyGP_7 Inductive crosstalk Inductive crosstalk depends on: –separation between traces according to the law –time derivative of the signal: –longitudinal length along which the traces run parallel higher crosstalk for short rise times or high frequencies

8. @ Copyright 1999 - F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyGP_8 Slots in ground plane In presence of a slot in ground plane: –return current cannot stay under signal trace: loop increased inductance Signal trace Return path Ground plane with a slot

9. @ Copyright 1999 - F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyGP_9 Additional inductance Additional inductance for the trace: Width q of the slot has almost no influence; in fact D is responsible for current diversion: –thin or large slots of same length have the same effect Slots towards one end of the trace have less effect Slot in ground plane Signal trace D q w

10. @ Copyright 1999 - F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyGP_10 Additional inductance Excess inductance due to slots slows down signal edges (increase of rise time)  SIGNAL Z0Z0 Z0Z0 L Rise time introduced by the additional inductance Total rise time of the received signal

11. @ Copyright 1999 - F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyGP_11 Additional inductance Excess inductance due to slots in lines with capacitive loads may cause problems on resonant behavior of circuits L RSRS C LOAD If Q > 1, the circuit rings If Q  1, the circuit response is damped with a rise time

12. @ Copyright 1999 - F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyGP_12 Two traces over a slot Strong overlap of return currents of the two traces –large mutual inductance –large crosstalk Ground plane with slot Signal trace 2 Return current of trace #1 Return current of trace #2 Signal trace 1

13. @ Copyright 1999 - F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyGP_13 Two traces over a slot High coupling for very close traces (d  D/2) Crosstalk depend on: –L M –time derivative of signal –coupling length Signal trace #2 Slot in ground plane Signal trace #1 D q w d Mutual inductance

14. @ Copyright 1999 - F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyGP_14 “Cross-finger” layout Ground and power distribution are non-solid. They are connected at crossings by bypass capacitors Top layer (+V CC ) Bottom layer (ground) Signal trace Return current path

15. @ Copyright 1999 - F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyGP_15 Advantages & disadvantages Solution’s advantages –double face layout only Solution’s disadvantages –inductance of the signal line is larger than for solid ground and power planes This solution is the best compromise that avoids solid copper planes

16. @ Copyright 1999 - F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyGP_16 “Finger” layout “Finger” layout is another configuration with non- solid power and ground planes Top layer (+V CC ) Bottom layer (ground) Signal trace Return current path

17. @ Copyright 1999 - F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyGP_17 Advantages and disadvantages Advantages –double face layout only Disadvantages –higher inductance of the signal line (larger also than “cross-finger” layout) Rule –due to high inductance, avoid this layout for high speed logic

18. @ Copyright 1999 - F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyGP_18 Guard traces Without guard trace G, crosstalk level in #2 due to a signal in #1 is proportional to 0 y #1 h Ground plane G#2 #1 #2 G GND

19. @ Copyright 1999 - F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyGP_19 Use of guard traces With guard trace, grounded on both sides, crosstalk level is divided by 2 Since acceptable crosstalk level is  1% of interfering signal, guard traces are seldom needed. In most cases it’s sufficient to separate the traces u.l. = unit length (y/h = 10)  crosstalk <1% In general, no need for center guard trace 4 u.l. 1 u.l. Ground plane

20. @ Copyright 1999 - F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyGP_20 Current paths All currents must return to their source V CC GND This configuration is enough for functionality but it’s BAD for EMC point of view (large loops  radiation)

21. @ Copyright 1999 - F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyGP_21 Current paths This configuration is GOOD for both functionality and EMC point of view V CC GND Always control current return paths

22. @ Copyright 1999 - F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyGP_22 Ground planes properties Best way to control high speed return currents is to use PCBs with copper planes: –best zero (ground) reference voltage –radiated emissions are reduced by 10-20 dB Rule of thumb –clock speed > 5 MHz –rise times < 5 ns Use multilayer with power and ground plane

23. @ Copyright 1999 - F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyGP_23 Next topic Crosstalk