Presentation is loading. Please wait.

Presentation is loading. Please wait.

High Speed Properties of Digital Gates, Copyright F. Canavero, R. Fantino Licensed to HDT - High Design Technology

Published byPiero Belforte Modified over 7 years ago

Similar presentations

Presentation on theme: "High Speed Properties of Digital Gates, Copyright F. Canavero, R. Fantino Licensed to HDT - High Design Technology"— Presentation transcript:

1 High Speed Properties of Digital Gates

2 @ Copyright 1999 - F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyHSP_2 Course outline Contents Digital Signal Model Non Ideal Behavior of Components High Speed Properties of Digital GateHigh Speed Properties of Digital Gate Ground Planes Crosstalk Power Distribution Terminations Digital design Power Power categories Quiescent vs. active dissipation Driving a capacitance load Overlapping bias current Speed Output switching time Changes in voltage Changes in current Ground bounce Packaging Ground bounce (packaging effects) Double clocking Ground bounce magnitude Ground bounce reduction Using decoupling capacitors Lead capacitance

3 @ Copyright 1999 - F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyHSP_3 Digital Design Paramount considerations: –low power –high speed –cheap packaging Power Speed Packaging Big impact on system performance

4 @ Copyright 1999 - F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyHSP_4 Power Real power dissipation is only indirectly related to I CC current. Data sheets often ignore: –power dissipation which occurs at high speeds; –power dissipated by driving heavy output loads. These effects can cause the power supply current to exceed the typical I CC rating Power dissipationData sheetTypical supply current (I CC )

5 @ Copyright 1999 - F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyHSP_5 Power categories 1 - Input power 2 - Internal dissipation 3 - Drive circuit dissipation 4 - Output power V CC Gnd TTL Inverter 13 2 4 - Active dissipation (P A ) - Quiescent dissipation (P Q )

6 @ Copyright 1999 - F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyHSP_6 Quiescent vs. Active Dissipation Data sheets most often quote quiescent power under no load: Active power is the extra energy, beyond quiescent power, dissipated when a logic circuit switches: –load capacitance –overlapping bias currents Sum of power consumption for each resistive element in the circuit

7 @ Copyright 1999 - F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyHSP_7 Driving a capacitance load Energy per cycle: Power expended in the driving circuit when charging up and down the capacitive load: NO net power is dissipated by the capacitor itself V CC CLCL R CHARGE R DISCHARGE GND Logic device with capacitive load

8 @ Copyright 1999 - F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyHSP_8 Overlapping bias current As the device switches from one state to another, Q1 and Q2 may simultaneously conduct for a brief instant, generating a current surge from V CC to GND which dissipates power The extra power dissipation due to overlapping bias currents is proportional to the switching cycle rate TTL inverter output drive circuit V CC GND Z LOAD Q1Q1 Q2Q2

9 @ Copyright 1999 - F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyHSP_9 Speed Practical problems in high-frequency design are not related to propagation delay but most often are related to the minimum output switching time Propagation delay 10% 90% Output switching time INPUT OUTPUT

10 @ Copyright 1999 - F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyHSP_10 Output switching time Faster switching time causes problems with: –return currents –crosstalk –ringing Two distinct mechanism: –effects created by sudden changes in voltage –effects created by sudden changes in current Independent of propagation delay

11 @ Copyright 1999 - F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyHSP_11 Changes in voltage Most of the frequency content of a digital signal lies below, where t r is the pulse rise time Too short rise time (high ) –pushes up the value of f knee, forcing the frequency response of a propagating pathway to be flat up to f knee –can cause crosstalk on a nearby circuit through the mechanism of mutual capacitance

12 @ Copyright 1999 - F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyHSP_12 Changes in current Sudden changes in current may cause crosstalk problems on a nearby circuit through the mechanism of mutual inductance R C V(t) I(t)

13 @ Copyright 1999 - F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyHSP_13 Ground plane V CC trace Ground connection Ground bounce Ground bounce: –traces effects –packaging effects Signal trace

14 @ Copyright 1999 - F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyHSP_14 Packaging With high-speed, packages may cause problems: –lead inductance –lead capacitance –heat dissipation

15 @ Copyright 1999 - F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyHSP_15 Ground bounce ( packaging effects ) The inductance of individual leads in a device package may create the so called ground bounce problem Ground bounce consist of shifts in the internal ground reference voltage due to output switching The ground bounce voltage V GND generally interferes with reception stage

16 @ Copyright 1999 - F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyHSP_16 Ground bounce ( packaging effects ) Input circuit, due to ground bounce, sees: Idealized logic die, wire-bonded to four pins of a DIP package V IN V CC C LOAD L GND V GND I DISCHARGE Ground Plane V INPUT

17 @ Copyright 1999 - F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyHSP_17 Double-clocking ( ground bounce ) Double-clocking results from differential input action in the clock circuit of digital gates. Internal to a flip-flop, for example, the clock input measures the difference between the chip’s clock pin and its ground pin: Due to ground bounce, signal currents flowing in the ground pin may cause big glitches on The flip-flop will reclock itself on these glitches

18 @ Copyright 1999 - F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyHSP_18 Double-clocking ( ground bounce ) External observations of the clock input show no kind of glitches; the problem is internal to the logic package The double-clocking error happens on DIP flip- flop packages which have very fast output drivers connected to heavy capacitive loads Surface-mounted packages are less susceptible to double-clocking

19 @ Copyright 1999 - F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyHSP_19 Ground bounce magnitude Switching voltage 10-90 % switching time Load capacitance or resistance Lead inductance Resistive load Capacitive load

20 @ Copyright 1999 - F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyHSP_20 Ground bounce magnitude  V and t r depend on the logic family’s switching characteristic Lead inductance strongly depend on package type. Three techniques are available: –wire-bond –tape automated bonding (TAB) –flip-chip

21 @ Copyright 1999 - F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyHSP_21 Ground bounce reduction Slowing down the output switching time Spreading the grounds out, evenly around the chip (not lumping them together) Using a separate ground reference pin for the input circuitry Using decoupling capacitances

22 @ Copyright 1999 - F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyHSP_22 Using decoupling capacitors I GND [A] Output waveform and ground current (octal transceiver)

23 @ Copyright 1999 - F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyHSP_23 Using decoupling capacitors SMD I DC Bypass capacitor GND VCC GND VCC SMD I DC Bypass capacitor GND VCC GND VCC SMD I DC Bypass capacitor GND VCC GND VCC Location of bypass capacitor

24 @ Copyright 1999 - F. Canavero, R. Fantino 50 mm 50 mm 1.5 mm Test point Material: FR4 epoxy glass sheet with 35 micrometer copper on both sides. Using decoupling capacitors Test device parameters

25 @ Copyright 1999 - F. Canavero, R. Fantino I max = 50 mA t r = t f = 1 ns 10nF 125mm 76 25mm 50mm C 36 10nF Using decoupling capacitors Bypass arrangement

26 @ Copyright 1999 - F. Canavero, R. Fantino V(36) V(76) 10100 Time [nsec] V(36) V(76) 20304050607080900 A B A: C at Node 76 B: C at Node 36 Using decoupling capacitors Simulated noise vs. capacitor location

27 @ Copyright 1999 - F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyHSP_27 Lead capacitance Stray capacitance between adjacent pins of a logic device can couple noise voltages onto sensitive inputs CMCM Logic package t r = 5 ns GND 75  termination Long transmission line Z 0 = 75 ohm

28 @ Copyright 1999 - F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyHSP_28 Lead capacitance C M = 4 pF (typical value) R = 37.5  (parallel impedance of Z 0 and 75  termination) Crosstalk problem becomes more serious if: –rise times get shorter –input connections impedance get higher

29 @ Copyright 1999 - F. Canavero, R. Fantino 7/6/2017Licensed to HDT - High Design TechnologyHSP_29 Next topic Ground Planes

Download ppt "High Speed Properties of Digital Gates, Copyright F. Canavero, R. Fantino Licensed to HDT - High Design Technology"

Similar presentations

CMOS Logic Circuits.

CMOS Logic Circuits.
ECE C03 Lecture 71 Lecture 7 Delays and Timing in Multilevel Logic Synthesis Hai Zhou ECE 303 Advanced Digital Design Spring 2002.

ECE C03 Lecture 71 Lecture 7 Delays and Timing in Multilevel Logic Synthesis Hai Zhou ECE 303 Advanced Digital Design Spring 2002.
   >>> 

   >>> 
MICHAEL CHIANG EECS 713 12/05/2013 Presenting: Capacitors.

MICHAEL CHIANG EECS /05/2013 Presenting: Capacitors.
Digital Integrated Circuits© Prentice Hall 1995 Interconnect COPING WITH INTERCONNECT.

Digital Integrated Circuits© Prentice Hall 1995 Interconnect COPING WITH INTERCONNECT.
04/11/02EECS 3121 Lecture 26: Interconnect Modeling, continued EECS 312 Reading: 8.2.2, 8.3.4 (text) HW 8 is due now!

04/11/02EECS 3121 Lecture 26: Interconnect Modeling, continued EECS 312 Reading: 8.2.2, (text) HW 8 is due now!
Nasty Realities EECS 150 – Lab6 Spring 2001 By Steve Fang.

Nasty Realities EECS 150 – Lab6 Spring 2001 By Steve Fang.
04/09/02EECS 3121 Lecture 25: Interconnect Modeling EECS 312 Reading: 8.3 (text), 4.3.2, 4.4.1-4.4.4 (2 nd edition)

04/09/02EECS 3121 Lecture 25: Interconnect Modeling EECS 312 Reading: 8.3 (text), 4.3.2, (2 nd edition)
Microcomputer Buses Outline –What is a Bus? –Interfaces –Open Collector Buses –Tristate Buses –Bus Contention –Transmission Lines Goal –Understand bus.

Microcomputer Buses Outline –What is a Bus? –Interfaces –Open Collector Buses –Tristate Buses –Bus Contention –Transmission Lines Goal –Understand bus.
Lecture 21, Slide 1EECS40, Fall 2004Prof. White Lecture #21 OUTLINE –Sequential logic circuits –Fan-out –Propagation delay –CMOS power consumption Reading:

Lecture 21, Slide 1EECS40, Fall 2004Prof. White Lecture #21 OUTLINE –Sequential logic circuits –Fan-out –Propagation delay –CMOS power consumption Reading:
Digital logic families

Digital logic families
IC packaging and Input - output signals

IC packaging and Input - output signals
Chapter 2 Operational Amplifier Circuits

Chapter 2 Operational Amplifier Circuits
Revised: Aug 1, 20031 EE4390 Microprocessors Lessons 29, 30 Welcome to the Real World!

Revised: Aug 1, EE4390 Microprocessors Lessons 29, 30 Welcome to the Real World!
PCB Layout Introduction

PCB Layout Introduction
TDS8000 and TDR Considerations to Help Solve Signal Integrity Issues.

TDS8000 and TDR Considerations to Help Solve Signal Integrity Issues.
THE INVERTERS. DIGITAL GATES Fundamental Parameters l Functionality l Reliability, Robustness l Area l Performance »Speed (delay) »Power Consumption »Energy.

THE INVERTERS. DIGITAL GATES Fundamental Parameters l Functionality l Reliability, Robustness l Area l Performance »Speed (delay) »Power Consumption »Energy.
PCB Layout Introduction

PCB Layout Introduction
Chapter 07 Electronic Analysis of CMOS Logic Gates

Chapter 07 Electronic Analysis of CMOS Logic Gates
Digital Integrated Circuits© Prentice Hall 1995 Interconnect COPING WITH INTERCONNECT.

Digital Integrated Circuits© Prentice Hall 1995 Interconnect COPING WITH INTERCONNECT.

Similar presentations

Ads by Google