1. 21/12/2015Spicy Schematics & Circuit Simulation ­ Design Report © 2011­2013 iSchematics.com Home Spicy SWAN Design Report https://www.ischematics.com/webspicy/report.py?RCODE=37681421005154202555aswww.ischematics.com/webspicy/report.py?RCODE=37681421005154202555as1/41/4

2. 21/12/2015Spicy Schematics & Circuit Simulation ­ Design Report © 2011­2013 iSchematics.com * 2014­12­08­03­58­54 ******************HEAD********************* *SWAN/DWS Netlist and simulation file *Copyright 1985­2015 Piero Belforte and Giancarlo Guaschino *Generated by: SPICY SWAN (ischematics.com) *File: SPA_DIFF_COUPL_FREQ8 ****************************************** *Author: pierobelforte *Date: Dec 08 2014 *Desc: FREQUENCY RESPONSE OF *DIFFERENTIAL 60CM 100 OHM *STRIPLINE MODELED AS *ONE BTM PWL BLOCK. ******************ENDHEAD****************** *CKT START V0 17 0 PULSE(0 20GIG 0us 200us) X1 11 3 PEAK_DETECT X2 11 13 10 PHASE_METER_180 R1 14 15 50 X3 17 14 13 VFREQ_SWEEP_50_SOFT R0 11 0 100 X4 7 8 PEAK_DETECT X5 15 13 19 PHASE_METER_180 E_DIFF 7 0 15 6 1.0 0N X0 17 6 9 VFREQ_SWEEP_50_SOFT R2 6 0 50 X6 15 11 DIFF_STRIPLINE_60CM_SPAR_CORR * {RS} N_8=1 N_9=2 N_S21_AMPLITUDE=3 N_6=4 N_4=5 UN_13=6 UN_10=7 N_S11_AMPLITUDE=8 UN_15=9 N_S21_PH ****************************************** *MODELS USED IN CIRCUIT ****************************************** ********************** *Spicy SWAN ­ SWAN Model File *http://ischematics.comhttp://ischematics.com *Author: pierobelforte * Date: Sat 12 Apr 2014 05:34:37 GMT *Notes: ********************** * * {RS} N_IN=2 UN_3=3 N_OUT=4 N_3=5.SUBCKT PEAK_DETECT 2 4 E0 3 0 2 0 1.0 P0 3 4 ­1 0 0 0.001 1GIG *TAU=500ns C0 4 0 500p R1 4 0 1K ****************************************** *MODELS USED IN CIRCUIT ******************************************.ENDS ********************** *Spicy SWAN ­ SWAN Model File *http://ischematics.comhttp://ischematics.com *Author: Piero Belforte * Date: 14 June 2014 14:42:04 GMT *Notes: 0 to +­180 degrees *PHASE METER *IN THRESHOLD SET * TO 1e­12V. *START­STOP *IMPLEMENTATION. *IN THRESHOLD SET * TO 1e­12V. ********************** * * {RS} UN_18=2 UN_12=3 UN_13=4 UN_10=5 UN_11=6 UN_17=7 UN_14=8 UN_15=9 N_IN1=10 N_IN2=11 N_GEN=12.SUBCKT PHASE_METER_180 10 11 14 * IN1 IN2 OUT E0 15 0 10 0 THR(1E­12 0 1) 0N 1 R4 16 13 1K C0 13 0.1n E__180 14 0 13 0 PWL(0 0.5 180.5000000001 ­180 1 0) E3 5 0 15 6 THR(1E­12 0 1) 0N 1 E_DEL4 3 0 15 0 1.0 1F X9 5 4 16 8 SLOGIC_RSFF E_DEL8 6 0 3 0 1.0 1F E10 9 0 11 0 THR(1E­12 0 1) 0N 1 E11 4 0 9 7 THR(1E­12 0 1) 0N 1 E_DEL12 2 0 9 0 1.0 1F E_DEL13 7 0 2 0 1.0 1F ****************************************** *MODELS USED IN CIRCUIT ****************************************** ********************** *Spicy SWAN ­ SWAN Model File https://www.ischematics.com/webspicy/report.py?RCODE=37681421005154202555aswww.ischematics.com/webspicy/report.py?RCODE=37681421005154202555as2/42/4

3. 21/12/2015Spicy Schematics & Circuit Simulation ­ Design Report © 2011­2013 iSchematics.com *http://ischematics.comhttp://ischematics.com *Author: pierobelforte * Date: Fri 16 May 2014 13:13:53 GMT *Notes: ********************** ** {RS} N_OUT=1 ****************************************** *MODELS USED IN CIRCUIT ****************************************** ********************** *Spicy SWAN ­ SWAN Model File *http://ischematics.comhttp://ischematics.com *Author: Piero Belforte * Date: Fri 16 May 2014 09:09:21 GMT **********************.SUBCKT SLOGIC_RSFF 2 11 5 10 *SET=2 RESET=11 Q=5 Q_BAR=10 ****************************************** *Author: Piero Belforte *Date: Wed Mar 20 2013 *Desc: SR Flip Flop implemented by 2 *2­INPUT Ideal NOR GATES ****************************************** V0 8 0 DC(1) R0 8 9 11 0 THR(.5 0 10GIG) R1 9 5 10 0 THR(.5 0 10GIG) R2 5 0 1 V3 3 0 DC(1) R3 3 4 5 0 THR(.5 0 10GIG) R4 4 10 2 0 THR(.5 0 10GIG) R5 10 0 1.ENDS SLOGIC_RSFF.ENDS PHASE_METER_180 ********************** *Spicy SWAN ­ Model File *http://ischematics.comhttp://ischematics.com *Author: Piero Belforte * Date: Tue 05 Nov 2013 17:08:40 GMT **********************.SUBCKT VFREQ_SWEEP_50_SOFT 10 20 21 ** F_IN=10 OUT=20 VREF=21 *VOLTAGE SWEPT FREQ: EHALF 30 0 10 0.5 VF 40 0 SIN( 0 2V V(30) ) RF 21 20 50 *modulating out voltage (soft start,50ns) EF 21 0 40 * 50 1 *soft start (100ns) VSOFT_START 50 0 PULSE( 0 1 0ns 100ns).ENDS VFREQ_SWEEP_50_SOFT ********************** *Spicy SWAN ­ Model File *http://ischematics.comhttp://ischematics.com *Author: pierobelforte * Date: Sun 07 Dec 2014 19:16:55 GMT **********************.SUBCKT DIFF_STRIPLINE_60CM_SPAR_CORR 1 2 *IN OUT *DIFFERENTIAL MODE PWL MODEL FROM ZYT200 VF MODEL B_60CM_STRIPLINE_PWL 1 0 2 0 S11=PWL( + 0.00ns ­0.0101 0.186ns ­0.00498 0.379ns ­0.00201 + 0.649ns 0.00170 0.957ns 0.00394 1.31ns 0.00643 + 2.00ns 0.0117 2.652ns 0.01441 + 3.443ns 0.01822 4.474ns 0.02290 5.533ns 0.02707 6.564ns 0.03113 + 7.502ns 0.03420 7.788ns 0.03728 8.946ns 0.03489 + 9.345NS 0.03449 10.61NS 0.03259 11.97NS 0.03085 14.04NS 0.02975 + 16.05NS 0.02848 18.01NS 0.02785 20.00NS 0.02722 50NS.0275 100NS.0275) + Z0=100 TD=0n + S21=PWL( + 0ps 0 13.1ps 0.0145 23.7ps 0.0561 36.0ps 0.125 + 46.5ps 0.202 61.1ps 0.302 78.1ps 0.397 99.8ps 0.497 + 131ps 0.593 163ps 0.659 192ps 0.698 230ps 0.740 + 277ps 0.773 331ps 0.801 431ps 0.836 531ps 0.856 + 0.672ns 0.878 0.891ns 0.898 1.13ns 0.913 1.49ns 0.926 + 1.99ns 0.935 2.49ns 0.942 2.99ns 0.948 3.99ns 0.953 + 5ns 0.958 6.45NS 0.963 8.91NS 0.968 13.7NS + 0.971 17.3NS 0.972 22.3NS 0.973 29.3NS 0.974 93.8NS 0.975 + 100NS.975) Z0=100 TD=3.75n.ENDS DIFF_STRIPLINE_60CM_SPAR_CORR *CKT END ****************************************** *Simulations *Note: This portion below is updated when you simulate ******************************************.OPTIONS DELAYMETH=INTERPOLATION https://www.ischematics.com/webspicy/report.py?RCODE=37681421005154202555aswww.ischematics.com/webspicy/report.py?RCODE=37681421005154202555as3/43/4

4. 21/12/2015Spicy Schematics & Circuit Simulation ­ Design Report © 2011­2013 iSchematics.com https://www.ischematics.com/webspicy/report.py?RCODE=37681421005154202555aswww.ischematics.com/webspicy/report.py?RCODE=37681421005154202555as4/44/4 Copyright © 2011­2015 iSchematics LLC [circuit, simulation, simulator, ipad, ios, schematics, schematic, pspice for ipad, spice for ipad, spice for ios, schematic capture, circuit design, circuit design on ipad, circuit design for ipad, circuit simulation, circuit simulation for ipad, circuit simulation on ipad, electronics, electronic, Spicy Schematics, tablet, tablets, mobile, touch, ipad circuit simulator] iPhone and iPad are trademarks of Apple Inc..TEMP 27.TRAN TSTEP=5e­12 TSTOP=200e­6 TSTART=1e­6 LIMPTS=5000 V(17) V(3) V(10) V(8) V(19).END