1. By Piero Belforte, July 2010

2. Preface In the early 70s CSELT Labs (Turin,Italy) developed the first digital switches deployed in the Italian network. The Switching Techniques lab, headed by Piero Belforte, had the mission of developing a modular technology for fast prototyping of high-speed digital systems A CAD methodology for prediction of high-speed interconnects behavior was strongly needed…

3. The environment (1) IBM’s ASTAP circuit simulation program was only available on mainframe computers. ASTAP was very slow and inaccurate dealing with trasmission line and propagation effects. Accurate models of ICs I/O ports were not available.

4. The environment (2) The expression “Signal Integrity” didn’t exist. The IBIS models of Ics were not yet invented. The S-parameter concept was only used in the Microwave field in the frequency domain. The Eye-Diagram representation of digital signals was only used in the Transmission System domain.

5. The environment (3) HP launches the first desktop calculators (9800 series). Tek 7S12 TDR unit has already a 25 ps risetime capability. HP introduces the HPIB instrumentation control bus. DSP techniques were already known but never applied to circuit simulation.

6. Hp 9800 Series technology http://www.hpmuseum.org/tech98xx.htm http://www.hpmuseum.org/tech98xx.htm 8MHz 16-bit processor. Microcode stored in bipolar ROM (7 ICs were used to supply 256 28 bit words.) Firmware stored in 4K bit ROM chips organized as 512 8 bit words. Intel 1103 1K bit PMOS dynamic RAM ICs. 16-character LED display Philips cassette magnetic-tape cartridge drive HPL algebraic programming language HPIB bus card for instrument control

7. The TEK 7S12 TDR/Sampler Unit (25ps rise time)

8. THE WINNING IDEAS 1) Apply DSP (Digital Signal Processing) techniques to circuit simulation. 2) Use Wave variables instead of classical voltage and currents to model propagation effects. 3) Use TDR as Time-domain S-parameter extractor from actual devices. 4) Integrate Modelling & Simulation Environments using a Desktop calculator for both controlling instruments and runnig simulations. 5) Extensive use of PRBS sequences as stimulus and EYE- DIAGRAMS to evaluate signal prameters ( eye opening, jitter, Noise margins).

9. Piero (left) and his colleague Giancarlo (right) with the HP9821 desktop calculator used for the first versions of the simulator (circa 1974)

10. Published paper showing the Digital Wave DSP algorithms used for modelling and simulation of high-speed interconnects

11. Cellular topology (N transmission-line cells) interconnection structure modelled by the DWN program

12. Digital Network model of the cellular interconnection structure

13. DWN Simulation Program features The whole DWN algorithm for the modular structure required about 250 lines of HPL code and was written by Ugo Colonnelli. The output waveforms were plotted on a HP 9862A plotter driven by the calculator. The accuracy and speed performance was much better than IBM’s ASTAP circuit analysis program running on a mainframe computer.

14. Layout of a microstrip test circuit used for validation of simulator’s results (TDR response )

15. Plot of simulated (s) and measured (m) one-port TDR responses of the test circuit (1975 )

16. Simulation (s) vs measure (m) of a 220 Mbit/s MECL III pcb interconnect (1975) using a PRBS stimulus

17. ECL multi-drop backplane bus

18. Simulated and measured Eye-diagrams of the multi- drop bus carrying a 100Mbit/s PRBS stream (1975 )

19. Early HPIB automatic bench for modelling active and passive device based on Tek 7S12 TDR (1974)

20. Automatic I/O model extraction from biased TDR measures (S-parameters) of IC ports

21. THICK-FILM HIGH-SPEED HYBRID CIRCUIT

22. Thin-film hybrid clock driver designed for 500Mhz clock distribution

23. MEASUREMENT SETUPS FOR TDR I/O CHARACTERIZATIONS OF HYBRID CLOCK DRIVERS

24. BIASED TDR INPUT RESPONSES

25. BIASED TDR OUTPUT RESPONSES

26. TEST BOARD FOR TDR CHARACTERIZATION

27. DWN simulations of 250Mhz clock waveforms of the hybrid clock driver at various fan outs

28. 250 Mbit/s module designed using the DWN methodology (1974)

29. Backplane twisted pair interconnects among high-speed modules

30. COLLECTION of hybrid circuits designed and characterized using DWN (1973-1975)

31. Interconnect optimization for a high-speed (.5 Gbps) MCM using simulated eye diagrams (1975)

32. .5 Gbps MCM module fully designed by means of DWN modelling and simulations (1975)

33. Low-cost high-speed module for fast prototyping of digital systems fully optimized by DWN (1978)

34. EYE-DIAGRAM PARAMETERS FOR INTERCONNECT PARAMETERS EVALUATION

35. TDR Characterization of the connector

36. TLM model of the connector (DWN simulation)

37. SETTING OF INTER-MODULE BACKPLANE INTERCONNECT RULES BY SIMULATION

38. INTER-MODULE CLOCK INTERCONNECT PARAMETERS VS FREQUENCY (From DWN SIMs)

39. High-speed prototype of a digital switch built up using.5Gps modules

40. TEST SETUP OF A HIGH-SPEED DIGITAL SUBSYSTEM PROTOTYPE

41. WEB LINKS (1) http://it.linkedin.com/in/pierobelforte http://www.slideshare.net/pierobelforte http://sites.google.com/site/pierobelforte/Home/pier o-s-papers-1 http://sites.google.com/site/pierobelforte/Home/pier o-s-papers-1 http://www.linkedin.com/groups?mostPopular=&gid= 2673743 http://www.linkedin.com/groups?mostPopular=&gid= 2673743 http://docs.google.com/viewer?a=v&pid=sites&srcid= ZGVmYXVsdGRvbWFpbnxwaWVyb2JlbGZvcnRlZG9jf Gd4OjMwNzY5MjUzZjM1ZTJjNzQ http://docs.google.com/viewer?a=v&pid=sites&srcid= ZGVmYXVsdGRvbWFpbnxwaWVyb2JlbGZvcnRlZG9jf Gd4OjMwNzY5MjUzZjM1ZTJjNzQ

42. WEB LINKS (2) http://www.hp9825.com/html/hpib1.html http://www.hp9825.com/html/hp_9810_20_30.html http://www.hpmuseum.org/hp9820.htm