Andrew Young SLAC TID-AIR Technology Innovation Directorate

SLAC xTCA Accelerator Control systems ATCA for SLAC controls and also uTCA systems for others
Andrew Young SLAC TID-AIR Technology Innovation Directorate Advanced Instrumentation for Research Division

Outline LCLS-I and LCLS-II Overview ATCA versus uTCA SLAC ATCA for LCLS-I and LCLS-II and other applications SLAC’s mTCA designs DESY’s mTCA LLRF designs Q&A

SLAC Mission Readiness (LCLS-I upgrade)
SLAC “mission readiness” project has developed a full control system for pulsed room temperature accelerators (120 Hz), ATCA LLRF, femtosecond synchronization, machine protection, instrumentation and control. Embedded MRF timing and beam synchronous acquisition EPICS interface High reliability design Telecom crates Operates in the SLAC gallery without temperature control: 5-45C range. Design max operation 50C air temperature Hot swap to allow technicians to replace cards Redundant power supplies supported if needed

LCLS-II Accelerator Block Diagram
The LCLS-II is a CW superconducting linac driven X-ray free electron laser under construction at SLAC. The high beam rate of up to 1MHz, and ability to deliver electrons to multiple undulators (see figure below) and beam dumps, results in a beam diagnostics and control system that requires real time data processing in programmable logic. The soft x-ray undulator (SXR) line with 28 undulators optimized for a photon energy range from 0.2 keV to 1.3 keV plus a hard x-ray undulator (HXR) line with 38 undulators designed for a photon energy range from 1.0 keV to 25.0 keV.

ATCA and uTCA Background
In the beginning, SLAC had started with uTCA designs Original proposed for LCLS-II (new SLAC FEL, 1 MHz) and for upgrade of existing FEL (LCLS-I, 120 Hz) Designed and delivered systems for other applications (e.g. Pohang BPMs, delivered in 2016) After evaluation, SLAC then switched to ATCA from uTCA as the common platform LCLS-I accelerator controls upgrade, called “Mission Readiness”, 120 Hz machine, upgrade from VME and CAMAC ~80 LCLS-I LLRF stations (pre-production station already running in LCLS-I) ~80 BPMs (pre-production station already running in LCLS-I) Bunch Length Monitor LCLS-II high-performance system (1 MHz machine) Timing, BPM, other beam diagnostics systems, Machine Protection (all development close to completion) Other applications

ATCA and uTCA example Crates shown would each support 12 BPMs
ATCA crate 1 shelf for network and CPU 6 Carrier cards (FPGA) 12 AMC cards (A-D, D-A analog front end) 6 RTM cards (interlocks, slow analog) Crates available from 1 to 14 shelves Telecom industry standard hardware and backplane, redundant fan and power supply units Custom application cards uTCA.4 crate 12 full width AMC cards (typically FPGA and A-D / D-A) 12 full width RTM cards Typically analog front end Crates available from 2-12 slots Physics extensions to standard uTCA platform Crates shown would each support 12 BPMs

Comparison ATCA Common Platform Backplane: Carrier Cards: AMC cards:
uTCA.4 for Physics Several variants, most typical described below: Backplane: PCIe for data from CPU to AMC cards. Individual trigger lines from timing receiver to AMC cards AMC cards: FPGA and A-D / D-A on one card management Analog connections to matching RTM card. RTM cards: Analog / RF front ends IO connections ATCA Common Platform Backplane: 10G Ethernet to switch 3.7G Ethernet for timing data stream distribution Carrier Cards: FPGA, memory, network, management AMC cards: Analog / RF front ends and A-D / D-A High speed analog I/O RTM cards: Interlocks Miscellaneous analog and digital IO. 1: Carrier Card + 2X RTMs 2: Crate 3: RTM

Motivation: Many Systems With A Common Need
LCLS-II High Performance Controls Systems (HPS) Beam Position Monitor (BPM) Bunch Charge Monitor (BCM) Bunch Length Monitor (BLEN) Machine Protection System (MPS) Timing Delivery System Analog / RF Common Platform Architecture LCLS-I Controls Upgrade Systems Beam Position Monitor (BPM) Bunch Charge Monitor (BCM) Bunch Length Monitor (BLEN) Low Level RF (LLRF) Other Systems & Experiments SSRL Low Level RF Upgrade Transition Edge Sensor Detector for Cosmic Microwave Background experiments and X-ray spectrometers SSRL booster LLRF (already handed off to SSRL) LCLS-II Front-End Enclosure Gas Detector LCLS-II experiment arrival time monitor LCLS-II injector and experiment laser lockers LCLS-II experiment femtosecond timing distribution system. Created a “common platform” for the various LCLS (I and II) controls systems While keeping it flexible enough for additional analog & RF detector systems

Leverage The Crate To Minimize Cabling
* Leverage The Crate To Minimize Cabling LCLS-I / LCLS-II Controls Overview IPMI 1 Gbps Epics Network Rack Mount Server Timing LCLS1 / LCLS2 IPMI Serial Internal Network MPS Network IPMI Ethernet Switch Card Slot 1 MPS / Timing Interface Card Slot 2 Timing Distribution (3.7 Gbps) IPMI Busses Not Shown BBFB Network MPS Internal Fast (3.7 Gbps) 10 Gbps Internal Network Local Clock Bus Payload Card Slot 3 Payload Card Slot4 Payload Card Slot 5 Payload Card Slot 6 AMC 0 AMC 1 AMC 0 AMC 1 AMC 0 AMC 1 AMC 0 AMC 1

ATCA Common Platform Features
Combine A-D / D-A and analog IO on the AMC cards Requirements typically tightly coupled Minimized analog signal path to reduce interference Analog / RF engineers develop AMC boards Combine FPGA, memory, IMPI controls on the Carrier card Digital engineers develop FPGA carrier cards Independent mixed signal front end, and processing upgrade paths. Ethernet backplane Each carrier operates as a separate system. Allows simple hot-swap and re-configuration. Systems can be transparently distributed among multiple crates if needed Does not require CPU in crate (but is an option). Distribute timing on backplane Serial timing data stream used on one of the secondary networks, distributed to all carrier cards Timing decoding performed in each FPGA – have full access to timing pattern. Works on standard MRF event system network. Naturally already integrated in ATCA cards running at SLAC Distribute MPS on backplane Use secondary network to provide independent path for machine protection Rear Transition Modules RTMs are usually simple, but contain a variety of miscellaneous functions including interlocks, slow A-D / D-A, motor drivers etc. Eliminate the need for external chassis in most systems. More volume for analog circuits and more panel space than on uTCA.4 Allows more room for RF shielding Added panel space usually allows more reliable cabling. (SMA with proper torque).

ATCA Approach To Crate Based Systems
In ATCA each card operates as an independent unit No need to power cycle or reboot the entire crate The crate is always powered Individual cards are powered on and off as needed Application cards can be hot swapped Multiple sub-systems can coexist without impacting each other during maintenance IOCs can remaining running while card is power cycled or firmware is updated Register access will time out with warnings until hardware comes back online CPU reboot is not required when cards are added or removed Crate maintenance can occur while the system is running N+1 power supply redundancy allows power supply hot swap IPMI redundancy allows shelf manager replacement during operation Fan trays can be replaced while system remains running Deploying a separate crate for each sub-system is not cost effective. Platform supports the coexistence of multiple systems operating independently!

ATCA Common Platform Use at SLAC
Operating or fully operational prototype stage Complete set of instrumentation and control for the room temperature LCLS-I LINAC upgrade LLRF, BPMs, timing, loss monitors, Machine Protection, laser lockers, etc. Approximately 180 carrier cards SLAC LCLS-II beam instrumentation BPMs, timing, loss monitors, Machine Protection, laser lockers, etc. Approximately 500 carrier cards Under development Femtosecond timing distribution SPEAR3 ring LLRF system Laser synchronization for FACET2 plasma accelerator work and ASTA ultra-fast electron diffraction system Non-accelerator projects X-ray cryogenic sensor array readout for LCLS2 instruments Used in a variety of other X-ray instruments CMB telescope readout

LCLS-II Chassis Example
Example deployment with 8 BPMs and 6 MPS beam loss monitors MPS link node card with BLMs ASIS 7 slot ATCA crate Possible to support 10 BPMs plus link MPS link node in 6U Low cost Single slot solution

ATCA Crate with 4 systems integrated in a single Crate
Timing System and MPS RTM is in the back of the crate Network Switch MPS digital input module BPMs LLRF SHM

ATCA Carrier Module Xilinx “Kintex Ultrascale”
AMC Carrier RTM Xilinx “Kintex Ultrascale” KCU040 or KCU060: 2760 DSP slices, 200Gbit bidirectional bandwidth for ADC / DACs Power supplies for AMC cards +3, +4, +/- 6, +/-15, +12 (9A) No switching supplies required on AMCs for most applications 8GB DDR3 memory (in addition to 3MB on-chip fast memory) Supports Common Platform networks and management Carrier card is very complex but a single design is used for all applications AMC BAY[1] DDR3 Zone 3 FPGA Zone 2 AMC BAY[0] 48V-to-12V Power Filter Zone 1

AMC Profile * ATCA card is cut out to allow for full height AMC cards.
ATCA Chassis AMC Card Cage ATCA Carrier AMC CARD ATCA/AMC Front Panel ATCA Carrier Plate ATCA card is cut out to allow for full height AMC cards. Provides for additional component height Provides good seperation between digital and analog sections Standard configuration for full height AMC card support as opposed to mid height (uTCA)

ATCA AMC Carrier Interconnects
* ATCA AMC Carrier Interconnects AMC 1 LVDS IO To/From RTM RTM External high speed networks & LVDS IO JESD High Speed Serial, LVDS IO & Clocks FPGA 8GB DDR3 RF Power REGs Zone 3 AMC 0 JESD High Speed Serial, LVDS IO & Clocks Zone 2 Backplane Networks And Clocking Board Power & IPMC Timing Crossbar LVDS IO To/From RTM Zone 1

Example Rear Transition Module (RTM)
MPS digital inputs Slow analog inputs Digital interlock outputs 8 SFP+ modules 2 for timing 6 for high speed networks RTM is application specific! Example shown is for LCLS-II crates where SLOT 2 will serve as the gateway to LCLS-II timing and MPS networks!. Other variants for different applications include; laser locker, low level RF, interlocks, trigger output etc.

Communication Protocols
10G Ethernet is used for flexible communication Firmware to firmware as well as firmware to software Higher level protocol required for reliable message delivery over UDP: RSSI Reliable SLAC streaming interface, based upon RUDP protocol RFC-908, RFC-1151, draft-ietf-sigtran-reliable-udp-00 Additional features added to support flow control Facilitates breakup of large transfers into MTU sized messages Message formats for register access, asynchronous interrupts and bulk data IOC CPU Application FPGA Application FPGA Software Application Firmware Application Firmware Application RSSI RSSI RSSI IP/UDP IP/UDP IP/UDP Ethernet Switched Network

Maximize Firmware Block Re-use
AMC 0 ADC / DAC Config AMC 0 IOs AMC 0 DACs AMC 0 ADCs AMC 1 ADC / DAC Config AMC 1 IOs AMC 1 DACs AMC 1 ADCs AMC 0 Config AMC 0 IO AMC 0 JESD TX AMC 0 JESD RX AMC 1 IO AMC 1 JESD TX AMC 1 JESD RX AMC 1 Config Application Firmware (HLS, SystemGen, etc) (Specific To Each Sub-System, all other firmware is provided by common platform) BSA Engine Diagnostic Engine To All Blocks MPS Interface Register Master (Debug) RTM Interface Timing Engine DDR3 Arbiter SW Memory Transfer Register Master MPS Fault Transfer Timing Receiver DDR3 Controller UDP/RSSI Engine UDP/RSSI Engine UDP/RSSI Engine IPMI MPS Network UDP Router Eth PHY & MAC RTM Digital & SFP Timing Stream Backplane MPS DDR3 Memory Backplane Ethernet Network IPMI

Apply The Same Approach To Software Re-use
* Apply The Same Approach To Software Re-use External Interface Layer (EPICS) All common layers of software and firmware are developed by the common platform sub-system Encourages reuse and minimizes parallel development For application development a suite of commonly libraries and application modules are available as well CPSW (Common Platform SW) i.e. Generic ADC/DAC driver Firmware FIFOs and memories All firmware and software is developed with re-use and portability as a goal Past projects developments with this design approach have helped in accelerating the LCLS-II HPS development Plan to open source firmware and software! Application Layer API Hardware Abstraction (CPSW) Software Link Layer Software Hardware Hardware Or Simulation Link Layer Hardware Or Simulation Device

Status: All final production modules
One ATCA carrier type (FPGA board) and ~7 AMC plug-in module types is ~all needed for 6 sub-systems, plus firmware/software Multi-use Digital IO AMC (MPS) LLRF AMC Timing Digital AMC (Timing) AMC plug-in 1 AMC plug-in 2 Common Carrier (FPGA board), all systems Status: All final production modules Multi-use ADC/DAC AMC (Timing, MPS, BLEN, BCM) ATCA: Advanced Telecommunication Computing Architecture Optical Transceiver AMC (MPS)

ATCA sub-systems Timing master and distribution sub-system
Have master ATCA timing module (using standard carrier board), fiber-fanout module, timing receiver integrated in carrier module FPGA, plus PCIe receiver interface modules (for conventional system interfacing) Works on standard MRF event system network. Naturally already integrated in ATCA cards running at SLAC Not included in this talk Machine protection sub-system (existing ATCA modules) LLRF sub-system See some intro on next slides Additional information could be presented in a separate presentation

ATCA AMC Low Level RF Controller
2 AMC cards on a single carrier 10X RF input channels 1X RF output channel 2X fast DC ADC (370Ms/s) 300MHz to 3GHz range with different oscillator daughter cards Minor changes to extend to 6GHz Clocks and LO phase-locked to timing reference system. FPGA provides closed loop RF control. Very low measurement noise 4.3 femtoseconds RMS in 1MHz bandwidth 1 femtosecond RMS in 1KHz bandwidth Status: Operational For more details: Separate presentation S-band Dan Van Winkle

ATCA BPMs Implementation for LCLS-II and LCLS-I upgrade

Stripline and Cold Button BPM Block Diagram & Interfaces
Two BPM’s serviced by on a single ATCA Common Carrier Board ATCA Common Carrier Board BPM Front-end AMC Board FPGA 2 x ADC 370Msps BPMs Vacuum Structure 4 BPM App. Firmware Calibration Trigger Common Platform Firmware Crate Timing Input BPM Front-end AMC Board Eth/UDP 10Gbps Eth/UDP Zone 2 BPMs Vacuum Structure 2 x ADC 370Msps 4 BPM App. Firmware Calibration Trigger MPS Output To MPS Board

Stripline and Cold Button BPM Board
2 micron resolution at 180pC BPM signal processing 300MHz, 30MHz BW filters Distributed amplification /attenuation for high linearity 370Ms/s ADC Calibration function Inject signals on BPM strips Measure induced signal in perpendicular strips Corrects for cable and electronics drifts Status: In Production

Stripline BPM LCLS-I beam test at 10pC

Resolution of Simulated 180pC
Simulated Stripline BPM single shot resolution at 180pC is 1.0micron calculated from 200 shots. The requirement is 20microns at 10pC this measurement is consistent with the requirement. We are a factor of 1.4 better than previous designs. Isolation between and cards and slots >90dB. Good SNR

Calibration Scheme / Performance
The timing system provides 5 microsecond gaps in the beam train for calibration. (needed for calibration above 200KHz beam rate). Used for successful LCLS-I BPMs (and other installations) Earlier versions had 2um resolution at 160pC, and 20um at 10pC Meets LCLS-II requirements.

Firmware Block Diagram

Firmware Testing- Slow readout
User can set a triggering rate and raw-waveforms along with timestamps and processed data are distributed (throttled to <400Hz). Set rate to 1Hz (approx); capture two software frames: ] PulseId are 16-bit words at index (0-based) Difference between the two frames is which exactly matches the divider rate for the ~1Hz rate in the MiniTPG.

Slow Readout waveforms
The waveforms of the raw signal and its FFT (verify there are no distortions which could indicate mis-formatting etc.) look OK. Simulator was set so that 1st channel is an 0.5 * amplitude of second channel. → u = (0.5-1)/(0.5+1) = -0.75 Vertical axis has equal amplitudes (→ v = 0) horiz. sum should be 0.75*vert. sum.

Calibration Calibration tone on Horiz. Stripline X blanked
Y reasonable

Software Block Diagram

Cavity BPM Block Diagram & Interfaces
Two BPM’s serviced by on ATCA Common Carrier Board In Tunnel ATCA Common Carrier Board Downmixer Chassis BPM Front-end AMC Board FPGA Cavity BPMs Vacuum Structure 3 3 4 x ADC 370Msps 3 BPM App. Firmware Reference Trigger Downmixer Chassis Common Platform Firmware Crate Timing Input BPM Front-end AMC Board Cavity BPMs Vacuum Structure 3 10Gbps Eth/UDP 3 Zone 2 4 x ADC 370Msps 3 BPM App. Firmware Reference Trigger MPS Output To MPS Board

Cavity BPM ADC (is general purpose common AMC)
4X 16 bit 370 Ms/s ADC TI ADC16DX370 One channel for read back of timing system for precision synchronization (sub-sample) 2X 16 bit 370Ms/s DAC TI DAC37J82 ADC/DAC clock DAC driven VCXO for locked or unlocked operation Low phase noise clock oscillator Fast trigger reference output 2X DIN, 2X DOUT Fiber output for triggering Status: In Production

SLAC 180pC test

SLAC 12pC test

ATCA Crate with 4 systems integrated in a single Crate
Timing System and MPS RTM is in the back of the crate Network Switch MPS digital input module BPMs LLRF SHM

Summary of ATCA at SLAC SLAC controls is based on ATCA
SLAC / LCLS Low Level RF upgrade 83 ATCA cards for SLAC LCLS operations Additional for SPEAR ring and FACET2 accelerator SLAC LCLS-II, Instrumentation Cavity BPMs, stripline BPMs, bunch length monitor, bunch charge monitor, machine protection, beam loss monitors Approximately 500 ATCA cards Cosmic microwave background telescope projects Approximately 100K sensor channels, 25 ATCA cards. LCLS-II cryogenic X-ray sensor Approximately 10K high bandwidth sensor channels, 10 ATCA cards. SLAC RF femtosecond timing system Laser locker, RF-over-fiber timing Approximately 30 ATCA cards

mTCA interfaces Webpage URL

Where is microTCA being used?
SLAC provided mTCA at SSRL Six BPMs delivered mTCA at PAL Stripline/Cavity BPMs with a WFO agreements with SLAC mTCA at ESS Stripline BPM/LLRF with a CRADA agreements with SLAC Non-SLAC provided mTCA at DESY 27 hardware projects for LLRF to piezo controller RTMs License agreements with commercial vendors mTCA at ANL Upgrading LLRF mTCA at FRIB-MSU General purpose FPGA mTCA at IHEP

Collaboration-Pohang Accelerator Laboratory
The PAL-XFEL is a 0.1-nm hard X-ray FEL project starting from 2011, which aims at providing photon flux higher than 1 x 1012 photons/pulse at 0.1 nm using a 0.2 nC / 10 GeV electron linac. The photon flux of 1 x 1012 at 0.1 nm corresponds to the FEL power of 30 GW with the pulse length of 60 fs in FWHM. Beam trajectory must be maintained within 5 µm at 250pC in the linear accelerator to obtain this resolution PAL XFEL would like to use the LCLS-II mTCA stripline BPM system

PAL Lasing

PAL Saturation 132 uJ Total X-ray at YAG

Scope and Goals of the WFO for PAL
The WFO agreement was a collaboration between the Pohang Accelerator Laboratory and SLAC National Laboratory to develop microTCA systems for BPMs. The Phase I system consist of 9 AMC modules, 9 RTMs, a power supply, MicroTCA Carrier hub (MCH), CPU, EVR with distribution chassis and a microTCA chassis. Goals of our trip was to commission the microTCA electronics, characterize the 3 BPMs at the ITF, run side by side measurement of the Libera system was successfully complete in June 2014. Phase II system consists of designing 144 Stripline BPM RTMs while Pohang Purchases ALL of the infrastructure components such as; a power supply, 19 MicroTCA Carrier hub (MCH), 19 CPU, 19 EVR with distribution chassis and a 19 microTCA chassis. Phase III system Consist of designing 55 Cavity BPMs electronics. This consisted of a new RTM to interface to SIS8300-L2 125 MHz ADC, new EVR distribution, down mixer chassis, and all mTCA infrastructure such as; a power supply MicroTCA Carrier hub (MCH), CPU, EVR with distribution chassis and a microTCA chassis.

mTCA BPM system

SIS with SLAC RTM MicroTCA.4 LLRF digitizer: SIS was designed for SLAC for a BPM application. It is 8 channel Digitizer, 14 bits, 250 MSPS max that uses AD9643 instead of AD9268 (125MHz) and Virtex VI with 2Gb of memory. 250MHz sampling clock will place the BPM signal in the middle of the Nyquist zone, thus maximize the signal captured.

SLAC BPM RTM Four processing channels, one calibration network.
Rear Transition Module: Four processing channels, one calibration network. Two variable attenuators and RF amplifiers to meet the 10pC to 1nC dynamic range requirement. Altera MAX-V CPLD controlling the self-calibration state machine and attenuator settings. First stage bandpass filter has 30dB attenuation at 362.5MHz and 40dB attenuation at 237.5MHz. High attenuation at the Nyquist zone edge to prevent signals from leaking into the next Nyquist zone.

New PMC EVR from Hytec with SLAC RTM

Infrastructure Cards WEINER PM Concurrent CPU AM310/302 NAT MCH PHYSIC

Pohang BPM System (Front view)

Pohang BPM System (Rear view)

Epic screens

Single Shot Resolution Plot of the BPMs at 180pC

PAL XFEL Cavity BPMs

PAL XFEL Cavity BPMs Parameters XY Cavity (Dipole Cavity)
Reference Cavity (Monopole Cavity) Mode TM110 TM010 Frequency GHz Loaded Q Factor 2000 – 3000 R/Q > 2 Ohms/mm > 12 Ohms Induced Voltage > 5 mV/pC∙mm > 20 mV/pC X/Y Cross Talk Level < -20 dB -

Downmixer and Cavity BPM Chassis (in Tunnel)

Cavity BPM uTCA In the Cavity BPM system, SIS8300-L2 module was used with a new transformer coupled BPM RTM. Since the IF Frequency is 40MHz, the signal was directly digitized`

Cavity BPM EDM

Cavity BPM single shot resolution at PAL

Collaboration-ESS Laboratory
The European Spallation Source (ESS) aims to be the brightest source of neutrons in the world for scientific research. By the end of this decade (operational ~2019) it will be generating long pulses of neutrons. These will be used in parallel experiments that will foster major advances from aging and health, materials technology for sustainable and renewable energy, to experiments in quantum physics, biomaterials and nano-science. This is equivalent to the SNS in America. ESS plans to design beam Position Monitors (BPMs) and Low-Level RF (LLRF) systems using microTCA platform.

SIS8300-KU Central Design Parameters MTCA.4
4 lane PCI Express Gen3 Connectivity 10 Channels 125 MS/s 16-bit ADC10 MS/s to 125 MS/s Per Channel Sampling Speed AC and DC Input Stage Internal, Front Panel, RTM and Backplane Clock Sources Two 16-bit DACs for Fast Feedback Implementation High Precision Clock Distribution Circuitry Programmable Delay of Dual Channel Digitizer Groups Gigabit Link Port Implementation to Backplane Twin SFP+ Card Cage for High Speed System Interconnects XCKU040-1FFVA1156C Kintex Ultrascale FPGA Dual boot MMC1.0 under DESY license LV91 2 GByte DDR4 Memory (flexible partitioning scheme) In Field Firmware Upgrade SupportZone 3 class A1.0, A1.0C or A1.1CO compatible (see below)

SLAC LLRF/BPM RTM PCB board
The Card contain 10 channel RF input (for superheterodyne receiver to 20MHz and 2 DC couple inputs), 2 DC coupled arbitrary waveform generated (DC-40MHz), LO input, clock input, trigger input. RF backplane compatible.

SLAC has built uTCA and ATCA BPMs
ATCA and uTCA BPMs SLAC has built uTCA and ATCA BPMs ATCA BPM performance is as good or better than uTCA BPMs More space for filters (more space on AMC cards) Better physical separation of channels Newer design, newer higher speed ADC’s In ATCA: 2 BPMs per FPGA carrier card ATCA is more economic per BPM channel SLAC has provided uTCA or ATCA BPMs

DESY European XFEL the European XFEL, the biggest X-ray laser in the world, has reached the last major milestone before the official opening in September. The 3.4 km long facility, most of which is located in underground tunnels, has generated its first X-ray laser light. The X-ray light has a wavelength of 0.8 nm—about 500 times shorter than that of visible light. At first lasing, the laser had a repetition rate of one pulse per second, which will later increase to 27,000 per second.

DESY Development for European XFEL
DRTM-DWC10 DAMC-TCK7 DRTM-VM2HF DRTM-VM2LF eRTM-LOG1300 DRTM-VM2LF DRTM-DS8VM1 DAMC-FMC20 DRTM-PZ4 DRTM-DWC8VM1 27 hardware projects, ~ 16 developed by DESY ~ 6 developed by Industry, ~ 5 joint effort DESY & Industry … DFMC-MD22 DAMC-DS800

Block Diagram of LLRF at DESY
There are 8 Cavities for feedback and one vector modulator

MicroTCA.4 LLRF digitizer: SIS8300
LLRF at DESY MicroTCA.4 LLRF digitizer: SIS8300 10 ch. Digitizer, 16 bits, 125 MSPS max Virtex VI Application firmware block diagram: to uTC

MicroTCA.4 LLRF controller: TCK7
LLRF at DESY MicroTCA.4 LLRF controller: TCK7 Kintex VII 12.5 Gbps throughput 8x SPF+ on front panel Application firmware block diagram: Reference: “High-Speed Data Processing Module for LLRF”, D. Makowski, et al., IEEE Transaction on Nuclear Science Communication with LLRF Master – slave Piezo Beam-based feedback Communication with others Toroid (beam charge) Beam monitors (arrival time, compression)

RF Backplane uRFB with uLOG RF Backplane L3 = 21 RF stations
Input: Reference RF signal (REFER) Generation of local oscillator (LO) Generation of clocks (CLK) Distribution of REFER, LOG, CLK RF Backplane L3 = 21 RF stations  42 crates equipped with uRFB + uLOG uLOG

DESY LLRF Crate Digitizers (SIS8300) Power module CPU Timing
Main controller (TCK7) Machine protection (DAMC2)

LLRF Crate Rear view Digitizers (SIS8300) Power module CPU Timing
Main controller (TCK7) Machine protection (DAMC2)

LLRF Presentation showed DESY LLRF uTCA designs For details about SLAC ATCA LLRF see separate presentation

* The End Thank You!

* Backup Slides Thank You!

Physics Extensions Standards
--Available from (free copies for members)

Software Guidelines Status
Standard Hot Plug Procedure SHPP Standard Device Model SDM Standard Hardware API SHAPI Standard Process Model SPM 90% 100% 100% 80%

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