Characterization of Circuit Components Using S-Parameters

Characterization of Circuit Components Using S-Parameters
Chapter 1

Topic S-Parameters S1P S2P Y-Parameters Components Wires Inductors
Resistors Capacitors S-parameter Extraction

One-Port S-Parameter Incident wave (V1+) is Vin/2 (as if Zin=RS)
Voltage at the input of the receiver is Zin/(Zin+RS)Vin Vin=V1-+V1+ V1-=Vin -V1+ V1-= Zin/(Zin+RS)Vin- Vin/2 =(Zin-RS)/[2(Zin+RS)]Vin V1-/ V1+ =(Zin-RS)/(Zin+RS)

One-Port S-Parameter Series RLC with resonant frequency at
Resistance at resonant frequency: RL

Design a Series RLC Resonant Circuit
L1=2.4 mH RS=50 Ω fres=1 MHz What is C1?

Design a Series RLC Resonant Circuit
L1=2.4 mH RS=50 Ω fres=1 MHz What is C1? C1=1/(Lω2res)

One-Port S-parameter Power reflected to the source Power delivered
to the load

Two-Port S-parameter Actual voltage measured at
Incident Wave generated by Vin Incident wave into the output port or wave reflected from RL Reflected wave Actual voltage measured at the input of the two-port network: V1++V1- the output of the two-port network: V2++V2-

Y-Parameters Yo=1/Zo

Calculate Y-Parameters Using ADS

Wires In the AWG system, the diameter of a wire will roughly double every six wire gauges. E.g.

Skin Effect (Eddy Current)

Skin Depth The skin depth is thus defined as the depth below the surface of the conductor at which the current density has fallen to about 37% of its surface current density.

Inductance of a Straight Wire
breadboard wire: 22 AWG or 25.3 mils in diameter. Each mil =25.4 um or cm. 5 cm of a No. 22 copper wire produce about 50 nH of inductance.

Resistors Carbon-composition resistor Wirewound resistor
Carbon-film resistor

Carbon-Composition Resistors
Carbon composition resistors consist of a solid cylindrical resistive element with embedded wire leads. The resistive element is made from a mixture of finely ground (powdered) carbon and an insulating material (usually ceramic). The resistance is determined by the ratio of the fill material (the powdered ceramic) to the carbon. Higher concentrations of carbon, a good conductor, result in lower resistance. The parasitic capacitance arises out small capacitance between carbon fill. More expensive than carbon film resistor.

Wirewound Resistors Wirewound resistors are commonly made by winding a metal wire around a ceramic core. The inductance is much larger than a carbon composition resistor Poor temperature drift coefficient Too much L and C to be useable at high frequencies

Carbon Film Resistor Less expensive than carbon-composition resistors
Can drift with temperature and vibration A carbon film is deposited on an insulating substrate, and a helix is cut in it to create a long, narrow resistive path. (Partially exposed)

Generic Resistor Model

Example 8.7 nH 8.7 nH 10K 0.3 pF Impedance associated
inductor is negligible At 200 MHz A 10 Kohm resistor looks like a resistor at 200 MHz.

Insert an Equation in ADS

Impedance at 200 MHz 10 Kohm At DC

Extract Resistance from Y11
=10 KΩ

Extract Capacitance (1)
Slope is constant!

Extract Capacitance (2)
C=Y11imag_deriv/2/π=1.88 pF/2/3.1416= pF

Generic Equivalent Circuit for a Capacitor
L: inductance of the leads Rp: account for leakage current

Quality Factor of a Simplified Capacitance Model
Quality factor= Im[Z]/Re[Z] =1/(ωRC)

Generic Equivalent Circuit for an Inductor
Series resistance +skin resistance

Extraction Example

Parasitic Resistance of an Inductor

Inductance Extraction
L=R/(2πfL) =29.73 nH

Parasitic Capacitance of an Inductor
Capacitance: fF

Quality Factor of a Simplified Inductor Circuit Model
Q=Quality factor= Im[Z]/Re[Z] = (ωL) /(R) Larger Q, better inductor

Additional Slides

Metal Film Resistor

Thin-Film Chip Resistor

Impedance Transformation

Topics Quality Factor Series to parallel conversion Low-pass RC
High-pass RL Bandpass Loaded Q Impedance Transformation Coupled Resonant Circuit Recent implementation, if time permits

Quality Factor

Quality Factor Q is dimensionless

Quality factor of an inductor
(Imax) 𝑃𝑑𝑖𝑠𝑠= 𝐼 𝑚𝑎𝑥 2 𝑅 2 ω= 2π 𝑇 →𝑇 = 2π ω 𝐸𝑑𝑖𝑠𝑠=𝑃𝑑𝑖𝑠𝑠𝑇= 𝐼 𝑚𝑎𝑥 2 𝑅 2 2π ω = 𝐼 𝑚𝑎𝑥 2 𝑅π ω 𝐿 𝑑𝐼 𝑑𝑡 𝐼 𝑑𝑡= 𝐿𝐼 𝑑𝐼= 𝐿𝐼 𝑚𝑎𝑥 2 2 Please note that Q is also equal to Q=Im(Z)/Re(Z) Q=(ωL)/R

Quality factor of Parallel RL circuit
Q=Im(Z)/Re(Z) Z= 𝑅𝑃||𝑠𝐿 𝑅𝑝+𝑠𝐿 = 𝑅𝑝𝑗ω𝐿 𝑅𝑝+𝑗ω𝐿 = 𝑅𝑝𝑗ω𝐿(𝑅𝑝−𝑗ω𝐿) 𝑅𝑝 2+ ω𝐿 2 Q=ωL(Rp)2/(ω2L2Rp)=Rp/ωL

Quality factor of a Capacitor
𝑃𝑑𝑖𝑠𝑠= 𝑣 𝑚𝑎𝑥 2 2𝑅 ω= 2π 𝑇 →𝑇 = 2π ω 𝐸𝑑𝑖𝑠𝑠=𝑃𝑑𝑖𝑠𝑠𝑇= 𝑣 𝑚𝑎𝑥 2 2𝑅 2π ω = 𝑣 𝑚𝑎𝑥 2 π ω𝑅 𝐶 𝑑𝑣 𝑑𝑡 𝑣 𝑑𝑡= 𝐶𝑣 𝑑𝑣= 𝐶𝑣 𝑚𝑎𝑥 2 2 Z is the impedance of parallel RC Please note that Q is also equal to Q=Im(Z)/Re(Z) Q=ωCR

Quality factor of a Capacitor in Series with a Resistor
Z is the impedance of series RC Please note that Q is also equal to Q=Im(Z)/Re(Z) Q=1/(ωCRS)

Low-Pass RC Filter

High-Pass Filter ωlpf=ωhpf 𝐿=𝑅2𝐶

LPF+HPF ωlpf=ωhpf

LPF+HPF (Magnified)

Resistor Removed

Design Intuition

Circuit Quality Factor

Mathematical Analysis

Transfer Function of a Bandpass Filter
Resonant frequency

Cutoff Frequency

Bandwidth Calculation
𝑄=ω𝑜𝑅𝐶

Equivalent Circuit Approach
At resonant frequency, XP=1/(ωoCp)

Effect of the Source Resistance
Q=3.162/(0.664)=4.76

Effect of the Load Resistor
6 dB drop at resonance due to the resistive divider. Q=3.162/( )=0.49 The loading will reduce the circuit Q.

Summary Q=0.99 𝑄=ω𝑜𝑅𝐶 Q=4.79 Q=0.49

Design Constraints Specs List Q, C & L Resonant Frequency: 2.4 GHz
RS=50 Ohms RL=Infinity List Q, C & L 𝑄=ω𝑜𝑅𝐶

Values Q C L 0.5 0.663 pF 6.63 nH 1 1.326 pF 3.315 nH 10 13.26 pF 331.5 pH Specs: Resonant Frequency: 2.4 GHz RS=50 Ohms RL=Infinity

Design Example Q=2.4/( )=10.12 BW=237 MHz

Implement the Inductor

Resistance of Inductor
R=Rsh(L/W) Rsh is the sheet resistance Rsh is 22 mOhms per square for W=6um. If the outer diameter is 135 um, the length is approximately 135um x4=540 um. R=22 mOhms x (540/6)=1.98 Ohms Q=(ωL)/R=(2π2.4G0.336 nH)/1.98 Ω=2.56

Include Resistor In the Tank Circuitry
Q=2.427/( )=2.04 Inclusion of parasitic resistance reduces the circuit Q from 10.

Series to Parallel Conversion

Series to Parallel Conversion
We have an open at DC! We have resistor RP at DC! It is NOT POSSIBLE to make these two circuits Identical at all frequencies, but we can make these to exhibit approximate behavior at certain frequencies.

Derivation QS=QP

RP QS=1/(ωCSRS)

Cp QS=1/(ωCSRS)

Summary

Series to Parallel Conversion for RL Circuits

Resistance of Inductor
R=Rsh(L/W) Rsh is the sheet resistance Rsh is 22 mOhms per square for W=6um. If the outer diameter is 135 um, the length is approximately 135um x4=540 um. R=22 mOhms x (540/6)=1.98 Ohms Q=(ωL)/R=(2π2.4G0.336 nH)/1.98 Ω=2.56 Rp=RS(1+QSQS)=1.98 Ohms(1+2.56x2.56)=14.96 Ohms Lp=LS(1+1/(QSQS))=331.5 pH(1+1/2.56/2.56)= nH

Insertion Loss Due to Inductor Resistance
At resonant frequency, voltage divider ratio is 14.96Ω/(14.96 Ω+50 Ω)=0.2303 Convert to loss in dB, 20log10(0.23)= dB

Use Tapped-C Circuit to Fool the Tank into Thinking It Has High RS

Derivation

Previous Design Values
Q C L 0.5 0.663 pF 6.63 nH 1 1.326 pF 3.315 nH 10 13.26 pF 331.5 pH Specs: Resonant Frequency: 2.4 GHz RS=50 Ohms RL=Infinity

Design Problem Knowns & Unknowns Knowns: RS=50 Ohms CT=13.26 pF
C1/C2 R’S

Calculations CT=C1/(1+C1/C2) C1=CT(1+C1/C2) C1/C2 R’S C1 C2 1 200 Ω
26.52 pF 2 450Ω 39.78 pF 19.89 pF 3 800Ω 53.04 pF 17.68 pF

Include the Effect of Parasitic Resistor

Filter Design (1) Jack Ou ES590

Outline Butterworth LPF Design Example LPF to HPF Conversion
LPF to BPF Conversion LPF to BRF Conversion

Butterworth Filter (Attenuation of the Butterworth filter)
Avoid ripples in the passband. As n increases, the responses assumes a sharper transition. The 3dB bandwidth remains independent of n.

Low Pass Filter Design Requirement
fc=1 MHz Attenuation of 9 dB at 2 MHz.

Determine the number of elements in the filter
9 dB of attenuation at f/fc of 2.

Low Pass Filter

Frequency and Impedance Scaling

Impedance Scaling

Simulation Results

Design Requirement for a Butterworth Low Pass Filter
The cut-off frequency is not known in this design specification.

Design Process Since f2=2f1, then n=3. (fo=1.45 MHz)

Elementary Prototype Value

Calculation of Component Values

Simulation Results

LPF to HPF Conversion

High Pass Filter Design Requirement
fc=1 MHz Attenuation of 9 dB at 0.5 MHz.

(fc/f) 9 dB of attenuation at fc/f of 2.

Low Pass Filter

LPF to HPF Transformation
Swap L with C, and C with L. 2. Use the reciprocal value.

(same as before)

Impedance Scaling

LPF to BPF Conversion

LPF TO BPF Conversion

Determine f3

Typical Bandpass Specifications
When a low-pass design is transformed into a bandpass design, the attenuation bandwidth ratios remain the same.

Determine n using f/fc

Transformation from LPF to BPF
The Actual Transformation from LPF to BPF is accomplished by resonating each low-pass element with an element of the opposite type and of the same value. All shunt elements of the low-pass prototype circuit becomes parallel resonant circuits, and all series elements become series-resonant circuits.

Transformation Example
Resonate each low-pass element with an element of the opposite type and of the same value.

Calculate Component Values

Fourth Order Butterworth Filter

Transformation

Component Calculation

Schematic

Av on Log(f)

Av on Linear f

Band Rejection Filter

LPF to BRF Conversion Substitute BWC/BW for fc/f
on the normalized frequency axis.

Design Example f1=2472.5 MHz f2=2472.72 f3=2494.28 f4=2494.5 MHz
(22)/(21.56)=1.0204 Center Freq: MHz

Determine # of Stages Hmm…. not enough suppression.

Design Example f1=27 MHz f2=45 MHz f3=75 MHz f4=125 MHz
(98)/(45)=2.1778 Thus fc/f=2 Center Freq: 58.1 MHz

Determine # of Stages fc/f

Transformation from LPF
Replace each shunt element with a shunt series resonant circuit. Replace each series element with a series parallel resonant circuit. Both elements in each of the resonant circuits have the same normalized value.

Component Calculations

Band Rejection Filter

LPF Elementary Prototype

BRF Transformation

Band Rejection Filter f1=27 MHz f2=45 MHz f3=75 MHz f4=125 MHz

Filter Design (2) Jack Ou ES590

Last Time Outline Butterworth LPF Design General Cases Other Filters
LPF to HPF Conversion LPF to BPF Conversion LPF to BRF Conversion General Cases Dual Networks RL≠RS Other Filters Chebyshev filter Bandpass Design Example Bessel filter Filter Synthesis via Genesis

fc=1 MHz Attenuation of 9 dB at 2 MHz. RS=50 Ohms RL=25 Ohms

(Same as before) 9 dB of attenuation at f/fc of 2.

Use a Low Pass Prototype Value for RS≠RL

Comparison: RS=RL

Matlab Calculation

Low Frequency Response

Comments about Butterworth Filter
A medium –Q filter that is used in designs that require the amplitude response of the filter to be as flat as possible. The Butterworth response is the flattest passband response available and contains no ripples.

Chebyshev Response Chebyshev filter is a high-Q filter that is used when : (1) a steeper initial descent into the passband is required (2) the passband response is no longer required to be flat

Comparison of a third order Passband Filter
3 dB of passband ripples and 10 dB improvement in attenuation

Design Methodology Even though attenuation can be calculated analytically, we will use the graphical method. Even order Chebyshev filters can not have equal termination (RS≠RL)

fc=1 MHz Attenuation of 9 dB at 2 MHz. RS=50 Ohms RL=25 Ohms Less than 0.1 dB of Ripple Design it with a Chebychev Filter

0.1 dB Attenuation Chart

0.1 dB, n=2, Chebyshev

Matlab Calculation

Chbysehv, 0.1 dB Ripple, LPF ripple

Butterworth Vs. Chebyshev
Butterworth: n=4, 40 dB Chebyshev: n=4, 48 dB, but RS≠RL We have to settle for n=5, 62 dB.

Chebyshev, 5th Order, 0.1 dB Ripple

Effect of Limited Inductor Quality Factor
Assume each inductor has a quality factor of 10.

Minimum Required Q

Phase of Chebyshev Bandpass Filter
Phase is not very linear during the passband! You can get a lot of distortion!

Bessel Filter Bessel Filter is designed to achieve linear phase at the expense of limited selectivity!

fc=1 MHz Attenuation of 9 dB at 2 MHz. RS=50 Ohms RL=25 Ohms

Attenuation Possible to achieve 9dB

Bessel LPF Prototype Elementary Value

Matlab Calculation

Bessel LPF 6.8 dB of attenuation at f/fc=2

Phase of Bessel LPF (n=2)

Genesys BPF Design Example

Butterworth Vs. Chebyshev
Butterworth: n=4, 40 dB Chebyshev: n=4, 48 dB, but RS≠RL We have to settle for n=5, 62 dB.

Start Geneysis Select Passive Filter Start Genesys

Filter Properties

Comparison Synthesized Via Genesis Synthesized using Charts

Change Settings

QL=50, QC=100

QL=10, QC=100

Export Schematic to ADS
(Not sure. ADS project is open)

Tune You can also fine-tune the value of a component and see how it changes the filter response

Impedance Matching (1)

Maximum Power Transfer
Choose an RL in order to maximize power delivered to RL.

Power Delivered to the Load

Numerical Example VTH=1 V RTH=50 Ω

Conclusion! Maximum power is delivered to the load resistor when RL is equal to RTH.

Max Power Transfer for Complex Source Impedance
At resonant frequency, the series impedance of the inductor and capacitor is zero.

Summary RL>RS RS>RL

L Network Different L netowrk Difference bewteen highpass and low pass
Examine butterworth filter from the point of view of matching….

Resistance Transformation
RP must be larger than RS (See derivation in the handout)

Matlab Calculation

Simulation Results

High Pass Match Note: There is not a DC path to ZL.
RS must be larger than RL! See derivation! QS=sqrt(RS/RL-1) QS=1/(ωRLC) QS=RS/(ωL)

Matlab Calculation

ADS Simulation

Dealing With Complex Load
Absorption Approach Resonance Technique

Match Via Absorption Approach
Ignore stray component Match the load resistance to the source resistance with an L-match Subtract the stray component from the L-match value

Absorption Example

Calculation Neglecting Stray Components

Account for Stray Components
This technique will not work if the stray components is much larger than L match components. E.g. if 2pF is replaced by 6 pF, then this technique will not work.

Resonant Approach Resonate any stray reactance with an equal and opposite reactance at the frequency of interest!

Example Resonate the 40 pF with a parallel L.

Parallel Resonant Network

Determine the Matching Network

Resonant Approach Example

Series to Parallel Conversion for RC Circuits

Series to Parallel Conversion for RL Circuits

Intuition If the Q is sufficiently large, LS≈LP and CS ≈CP.
RP is Q2 times RS.

Summary RL>RS RS>RL

Smith Chart Derivation

Smith Chart Derivation (2)

Smith Chart Construction
(+) (-) (The center line represents an axis where X=0.)

zL=1±j

Adding a Series Capacitance to an Impedance

Use Smith Chart Matching

SmithChartMatch

Smith Chart Utility 1. Select Smith Chart Match
Click on Tools, then select Smith chart utility 3. Select first option

Change the Load Impedance to 75 Ohms

Lock Load/Source Impedance

Add a Shunt Capacitance

Negative Capacitance! Negative capacitance

Add a Series Inductor (1) (2)
Double click on the smith chart to drop the component

Build ADS Circuit

Comparison with Matlab Vs. ADS
Shunt Cap 1.511 pF 1.5 pF Series L 5.72 nH 5.627 nH

Adding an Inductor in Series
Insertion of a series inductor to an impedance moves the impedance upward, causing a rotation clockwise along a constant circle of resistance

Series Inductance Low L High L Neg L fixed frequency

Adding a Capacitor in Series
Insertion of a series capacitor to an impedance move impedance downward, causes a rotation counter clockwise along a constant circle of resistance

Series Capacitance Neg C High C Low L fixed frequency Insertion of a series capacitor to an impedance move impedance downward, causes a rotation counter clockwise along a constant circle of resistance

Admittance

Admittance Example

Method 1

Method 2 1. Find the Z. 2. Rotate Smith Chart 180 degrees

Smith Chart Construction
Inductive susceptance (-) Conductance circle (+) Rotate the impedance chart by 180 degrees (The center line represents an axis where X=0.) Capacitive susceptance

Enable Admittance Chart

Adding a Shunt Capacitance
Insertion of a shunt capacitor causes a rotation clockwise along a constant circle of admittance

Neg C High C Low C fixed frequency Insertion of a shunt capacitor causes a rotation clockwise along a constant circle of admittance

Adding a Shunt Inductance
Insertion of a shunt inductor causes a rotation counter clockwise along a constant circle of admittance

Shunt Inductance Low L High L Neg Ind fixed frequency Insertion of a shunt inductor causes a rotation counter clockwise along a constant circle of admittance

Next Class Pi Network T Network Smith Chart Genesis

The Pi Network The virtual resistance must be less than RS and RL.

Impedance Matching (2)

Outline Three Element Matching Motivation Pi Network T Network
Low Q or Wideband Matching Network Impedance Matching on Smith Chart Two-Element Three-Element Matching Multi-Element Matching Genesis

RV=4.424 Ohms Component Q=4.73

Circuit Q Q of Vin/VS=102.2/(125.4-83.1)=2.416
Circuit Q is different from component Q! Q of Vout/VS=98/( )=2.21

Four Combinations of L-Match
RL>RS RS>RL

Split a Pi Network into Two L Networks

Virtual Resistor Virtual Resistance must be
smaller than source resistance! (Blocks DC) RL>RS RS>RL

Design a Pi-Match RS=100 Ohms RL=1000 Ohms Resonant Frequency: 100 MHz
R2/R=(Q22+1)/(Q12+1) (See attached) Q1 Q2

Calculation Design Sequence: Q1, Q2 RV L2, C2 L1, C1

Pi-Match Schematic

Use Pi-Match to Produce Matching at 100 MHz

T-Match

T-Match RL>RS RS>RL

Calculation in Matlab

Schematic Q1=10 Q2=4.472 RV=1050 Ohms

Vin/VS

Review of Smith Chart Adding an inductor in series
Adding a capacitor in series Adding a capacitor in parallel Adding an inductor in parallel

Adding an Inductor in Series

Adding a Capacitor in Series
Insertion of a series capacitor to an impedance move impedance downward, causes a rotation counter clockwise along a constant circle of resistance

Insertion of a shunt capacitor causes a rotation clockwise along a constant circle of admittance

Adding a Shunt Inductance
Insertion of a shunt inductor causes a rotation counter clockwise along a constant circle of admittance

Example Design a matching network with a source impedance of
25+15j Ohm and output impedance of j Ohms. (We need to have match the source and load to their complex conjugates)

Starting Smith Chart (source) (load)

Four Combinations of L-Match
(Series L causes clockwise Movement on constant R on smith chart… …) (The only one) RL>RS RS>RL

C=39.46 pF; L= nH

Constant Q Q of series impedance=ratio of reactance to resistance

Constant Q Circle

Example 4-4 Constant Q of 15 Q=15 The end of large terminating resistor will determine the Q.

Example 4-4 (Adding a Series L)
Get the admittance circuit with a series L

Example 4.4 Get back with the center of chart with a shunt cap.

Example 4-4 (Q=15)

Compare the Smith Chart Design with Calculation in Matlab
C2 (matlab) C2(Smith Chart) L1+L2 (matlab) L1+L2 (Smith chart) C1 (matlab) C1 (Smith chart) 23.87 pF 22.36 pF nH 147.9 nH 68.55 pF 75.49 pF

Example 4.8 Design a T network to match Z=15+15j Ohm source to a 225 Ohm load at 30 MHz with a loaded Q of 5.

Example 4.8 Get on Constant Q=5 curve

CMOS Transistors

Outline Qualitative Description of CMOS Transistor gm/ID Design
Biasing a transistor Using gm/ID Approach Design Using Cadence

A Crude Metal Oxide Semiconductor (MOS) Device
V2 causes movement of negative charges, thus current. V1 can control the resistivity of the channel. Positive charge attract negative charges to interface between insulator and silicon. A conductive path is created If the density of electrons is sufficiently high. Q=CV. P-Type Silicon is slightly conductive. The gate draws no current!

An Improved MOS Transistor
(provide electrons) (drain electrons) n+ diffusion allows electrons move through silicon.

Typical Dimensions of MOSFETs
These diode must be reversed biased. tox is made really thin to increase C, therefore, create a strong control of Q by V.

A Closer Look at the Channel Formulation
Need to tie substrate to GND to avoid current through PN diode. VTH=300mV to 500 mV (OFF) (ON) Positive charges repel the holes creating a depletion region, a region free of holes. Free electrons appear at VG=VTH.

Channel Resistance As VG increases, the density of electrons increases, the value of channel resistance changes with gate voltage.

Drain Current as a function of Drain Voltage
Resistance determined by VG.

Drain Current as a function of Gate Voltage
Higher VG leads to a lower channel resistance, therefore larger slope.

Length Dependence The resistance of a conductor is proportional to the length.

Dependence on Oxide Thickness
Q=CV C is inversely proportional to 1/tox. Lower Q implies higher channel resitsance.

Width Dependence The resistance of a conductor is inversely proportional to the cross section area. A larger device also has a larger capacitance!

Channel Pinch Off Q=CV V=VG-VOXIDE-Silicon VOXIDE-Silicon can change along the channel! Low VOXIDE-Silicon implies less Q.

VG-VD is sufficiently large
to produce a channel VG-VD is NOT sufficiently large to produce a channel No channel Electrons are swept by E to drain. Drain can no longer affect the drain current!

Regions (No Dependence on VDS) No channel

Determination of Region
How do you know whether a transistor is in the linear region or saturation region? If VDS>(VGS-VTH) and VGS>VTH, then the device is in the saturation region. If VDS<(VGS-VTH) and VGS>VTH, then the device is in the linear region.

Graphical Illustration

Limited VDS Dependence During Saturation
As VDS increase, effective L decreases, therefore, ID increases.

Pronounced Channel Length Modulation in small L

Transconductance As a voltage-controlled current source, a MOS transistor can be characterized by its transconductance: It is important to know that

What Happens to gm/ID when W and ID are doubled?

Body Effect The threshold voltage will change when VSB=0!

Experimental Data of Body Effect
The threshold voltage will increase when VSB increases.

Small Signal Model for NMOS Transistor

PMOS Transistor

IV Characteristics of a PMOS

Small Signal Model of PMOS

Small Signal Model of NMOS

gm/ID Design Approach

gm/ID Design Optimization
gm/ID Design Flow Specs Design Equations (Analytical) gm/Id Data Set (Emprical) The gmoverid design flow is a technique that allows engineers to size up transistors quickly and accurately without using complicated transistor models. It was published by Silveira and his colleagues back in 1996. A typical gmoverid design flow goes like this: You start with the specs. You express your specs in terms of a set of design equations, you then use query the gmoverid data base to obtain optimum W/L that satisfy the constraints. gm/ID Design Optimization (F. Silveira, JSSC, 1996.) W/L Ratios

Intuition gm gds gm/ID gm/gds 2gm 2gds gm/ID gm/gds 2gm 2gds gm/ID
How does it work? This figures shows a transistor which has a transconductance (gm), a drain-to-source conductance (gds), and a current (I) when biased at a gate-to-source voltage (VGS) and a drain-to-source (VDS). If an identical device is connected in parallel so that both devices are biased at the same VGS and VDS, both devices have the the same gm, gds and the same ID. Since the devices are connected in parallel, they can be treated as one device with an aspect ratio of 2W=L. The effective transconductance over current ratio is gm/ID for both the merged device as well as the stand alone device because gm and ID are doubled. The drain-to-source transconductance is also doubled for the merged device. As a result, the intrinsic gain (gm/gds) is identical for both the stand alone device and the merged device. It can therefore be stated that as long as transistors are biased at the same gm/ID, they will have the same gm/gds. This observation is true for two small signal parameters whose ratio depend solely on the gm/ID and not on the width of a transistor. Once a transistor of a given width (W) is characterized over a range of gm/ID, the gm/ID based parameters can be generalized to a transistor of an arbitrary width. gm/ID methodology will hold as long as a parameter of interest scales with W. gm gds gm/ID gm/gds 2gm 2gds gm/ID gm/gds 2gm 2gds gm/ID gm/gds

gm/ID Data Set gm/gds gm/gmbs ID/W Cgd/Cgg Cgs/Cgg ….more
(F. Silveira, JSSC, 1996.) What we have on this slide is a list of most commonly used gmoverid based parameters. gmovergds, for example, is the self-gain of a transistor. ID/W is the current density. The list goes on and on. How do we obtain the gmoverid data set? The gmoverid data set is not part of the standard design kit. You have to create it yourself by running DC simulation. You only have to generate the database once when you start a new design kit. We have shown in a previous paper that we can include additional parameters to enable gmoverid based noise simulation. We would like to add distortion parameters to enable nonlinear analysis.

Design Example

Calculation Initially assume that gmro is large! (gm is determined)

gm/gds (50)

Current Density

Biasing an MOS Transistor Using gm/ID technique
Section 7.1 J.Ou Sonoma State Univeristy

Basic Analysis Use 1.2 V (Modified Ex 7.1)

Design Equations

Assumption: VDD=1.2 V Transistor Information: Type: 120 nm Specify VDS Note var1_1 is ‘vsd’ if pmos is used Note var2_1 is ‘vns’ if nmos is used. In this example, is initially unknown, so we will assume that it is 0.0

Interpolation Since the database base can not be so large as to keep
all possible values of vds/vsb, we have to interpolate based on existing values, which are available On 0.1 V interval. Current release: need to enter inBias <= the minVar1 and maxVar1. minVar=maxVar-0.1

Browse Database dBrowse2D(25, 'pfet', '15.0u', 'vsd', 0.3, 0.4, 0.353, 'vns', 0.5, 0.6, 0.577, 'vth') Variable name=dBrowse2D(gmoverid, type, length, var1, minVar1, maxVar1,inBias1, var2, minVar2, maxVar2,inBias2, ‘parameter’ ) Valid parameters: gmovergds, gmovergmbs, vth, ft, gmoveridft, idoverw, vod, region, fndbderiv cgdovercgg,cddovercgg, cgsovercgg, csbovercgg, cdbovercgg, ron, vdsat, rseff, rdeff type: nfet, pfet length: {'120n' '180n' '250n' '350n' '600n' '800n' '1.0u' '2.0u' '3.0u' '4.0u' '5.0u' '6.0u' '7.0u' '8.0u' '9.0u' '10.0u' '15.0u' '20.0u'} (text string)

Iteration Start with Calculate length=‘120nm’ gmoverid=20
VDS=VDD/2, VSB=0 Calculate vod_1 vth_ vgs_1 vx (gate voltage) vs (source voltage) ID Idoverw W RD Vd Vds=Vd-Vs

Iteration Example

Design Iterations Iteration VS IDS W RD Vds 0.1 V 392uA 53.06 um
0.1 V 392uA 53.06 um 1.529Kohms 0.207 V 1 0.321 322 uA 45.16 um 1.89 Kohms 0.278 V 2 0.340 340.4 uA 46.86 um 1.762 Kohms 0.259 3 0.335 335 uA 46.44 1.788 Kohms 0.265

Matlab & Simulation Parameters Matlab Cadence W 46.56 um 46 um Vx
ids 336.8 uA 339 uA gm 6.7 mS 6.80 mS gm/ids 19.94 20.05 Vs 0.336 V 0.339 V Vd 0.6 V 0.593 V Vds 0.263 V 0.257V Vth 0.5 V 0.497 V

Circuit Design Using Cadence
J.Ou

Start Cadence Start Cadence

Create New Cellview

Add Instance

Add a Resistor

Add Ground

Add Power

Add Wire

Start ADE L

Start DC Analysis

Netlist and Run

Annotate DC Node Voltages

Model Library Setup

DC Voltage Annotated

Component Display

Display DC Operating Point
Click on the device to display values!

Save State

Low Noise Amplifier

DSB/SC-AM Modulation (Review)

Frequency Shift Property (Review)

Frequency Spectrum of DSB/SC-AM Signal (Review)

If the Receiver Uses a Different Frequency to Demodulate
(Keep by using with LPF)

Use an LNA Circuit to Reduce Noise
(11/20) (11/27) (12/4)

Design of a Low Noise Amplifier
1. Transistor Biasing 2. Add L1 (Ls) and Lg 3. Add Ls 4. Adjust Lg 5. Generate gate bias voltage 6. Add M2 7. Design the output resonant network 8. Reduce the quality of output tank!

Source Resistance (RS) is 50 Ω Assume a bias current of 1 mA Assumed: gm/ID=20 mS/mA

Determine M1 Initial assumptions: VDS1=0.3 V VSB=0 V (DC)
gm/ID=20 mS/mA ID=1 mA

gm/ID Calculation

Device Simulation

Add L1& Lg

Impedance Measurement
Our initial L1 and Lg does not produce a perfect match!

Increase Ls to Increase Real Impedance
(Increase Ls (or L1) to compensate For CGD)

(Ls=270 pH) (Ls=398 pH) (The resonant frequency is still off!)

Adjust Lg (fix at 3.5 GHz ) (Reduce Lg to increase the resonant freq)

Generate the Gate Voltage
Insulate the DC The resistor RB and CB isolate the signal path from the noise of IB and MB. Generate VGS of M1 (449.8 mV)

Find the width of MB

Determine RB RB must be much larger than RP, the parallel equivalent resistance Of RS. Otherwise, RB will load the input match network!

Input Bias Network!

Lg=14.85 nH, Ls=398 pH After adding the bias MB
Before adding the bias MB

Determine M2 (Choose M2 to be Identical to M1, for simplicity)
Also connect the gate of M2 to VDD.

Determine the Output Impedance
Use large L to provide DC bias and open at 3.5 GHz. Use an artificially large C to provide DC isolation and a short at 3.5 GHz. Use the port to calculate the S22 and output impedance.

Output Admittance Goal: to cancel the imaginary admittance with an inductor! An effective output capacitance of 135 fF An effective output resistance of 1/1.107mS=900 Ohms Since we know fo, and Ceff, we can calculate Leff: 15.3 nH

Adding Output Capacitance
A 15.3 nH inductor is too large to implement on silicon. We will add a 1 pF capacitor in parallel to reduce the required inductance to 1.82 nH

Schematic (A port is used to calculate the output impedance)
903~1/1.107 mS

Comparison of Smith Chart
Location of 3.5 GHz! After adding the bias MB After the output load The input resonant frequency also shifted.

Input Resonant Frequency Shifted to 3.15 GHz
We probably have to reduce Lg.

Real and Imaginary Part of Output Impedance

Adjust Lg to Move the Resonant Frequency to 3. 5GHz

S11 Using Lg of 10 nH

Input S11 Reflection coefficient larger than 1!
May have to adjust reduce the quality factor of the output tank!

Adjust Output Resistance

RL of 900 Ω

Transient Simulation

Trasient Simulation Vout=1.225-1.1745=50.5 mV
Vin= =1.67 mV Av=30.23, dB

Determine Parameters Using Matlab

DC Bias Simulation Purpose: Verify gm/ID DC parameters through simulation.

Source Resistance (RS) is 50 Ω Assume a bias current of 1 mA Assumed: gm/ID=20 mS/mA

Performance Parameters
Gain (convolution analysis) Port-to-Port Feedthrough (Noise) (Linearity)

Feedthrough Mechanism in a Mixer
(LO re-radiation)

Single Ended Pasive RF Mixer

Frequency Spectrum LO RF

LO-RF Feedthrough

Differential Mixer

Waveform

Voutp-Voutn

Frequency Spectrum

Comparison Reduced RF Feedthrough Reduced DC Offset

Double Balanced Passive Mixer

Waveforms

Frequency Spectrum No DC, RF, and LO Feedthrough

Output Waveform

Sampling Mixer

Sampling Mixer Rf: 100 Hz, LO: 400 Hz

Waveform of Sampling Mixer

DFT of the Output Spectrum

Use PMOS to Improve Sampling

Improved Sampling Due to PMOS

Output Spectrum of CMOS Switch

Characterization of Circuit Components Using S-Parameters

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