1. Embedded Design with The PPC 440 Processor Core
Xilinx Training

2. Welcome
If you are new to Embedded design with Xilinx FPGA’s, this module will explain why you may want to use the PPC 440 processor in the Virtex-5 FX FPGA family
Understanding the basics of the PPC 440 processor is essential if you are going to select an appropriate FPGA device family
The Embedded Developers Kit software (EDK) is designed to make building a fast embedded design easy

3. Objectives After completing this module, you will be able to:
Explain some of the benefits of the PPC 440 processor
Explain how the utilities included with the Embedded Developers Kit (EDK) are optimized for the PPC 440 processor
Explain how the Base System Builder makes it easy to make your embedded system

4. Lessons
Hardware Overview
PPC 440
Base System Builder
Summary

5. Xilinx Embedded Processor Innovation
PowerPC 440
Embedded Block with Integrated Interconnect
Performance
Integration
Flexibility
Features
PLB Embedded Development Kit IP
PowerPC 405
Hard Core
in Virtex-4 FX FPGA
PowerPC® 405
Hard Core
in Virtex®-II PRO FPGA
32-bit RISC
Processor
Soft Core
2000
2002
2004
2008
2006

6. Supported FPGAs FPGA families
Spartan-3/3A/3AN/3A DSP/3E FPGA (MicroBlaze processor)
Spartan-6 (MicroBlaze Processor)
Virtex-4 FX (MicroBlaze and PowerPC 405 processors) and LX/SX FPGA (MicroBlaze processor)
Virtex-5 FXT (MicroBlaze and PowerPC 440 processor) LX/LXT FPGA (MicroBlaze)
Virtex-6 (MicroBlaze processor)

7. Embedded Design in an FPGA
Embedded design in an FPGA can consist of the following
FPGA hardware design
Processor system
MicroBlaze processor (soft core)
PowerPC processor (PPC440 hard core)
PLB or PLB v46 bus
PLB bus components
Other FPGA hardware
Peripherals can either be custom made by the user with a Xilinx bus interface or a library of pre-optimized peripherals are available
Typically the FPGA contains logic that can be unrelated to the processor component of the design. This is part of the system-on-chip or single chip architecture concept.
Xilinx can support multiple processor instances. Each processor instance will have its own software platform that may or may not include a third-party operating system, such as Linux, or one of the many Real-Time Operating Systems (RTOS).
A software platform that does not include an OS will use the Xilinx Standalone platform that provides the basic software services.
The user software application is written from the aspect of main and performs the desired function.
Interrupt service routines may be part of the user application.

8. PowerPC Processor-Based Embedded Design
440 Core
Dedicated Hard IP
MCI
DMA
PPC DDR2 Memory Controller
DDR
TEMAC
The PPC 440 is integrated into the silicon of the FPGA. It interfaces with the outside world via a crossbar technology that consists of the following interfaces.
Memory Controller Interface (MCI): The PPC 440 processor supports an MCI port that is designed to connect directly to the PPC processor DDR2 memory controller. The separate memory interface improves system performance and enables access to larger memories.
Direct Memory Access (DMA): The PPC 440 processor also has four DMA ports. These are commonly used to connect to the tri-mode Ethernet MACs included with the Virtex-5 FPGA.
Processor Local Bus v46 (PLB v46): The PLB v46 interface supports a bus width of up to 128 bits of data. The PPC 440 processor supports both a master and two slave PLB v46 buses. The master bus allows the PPC 440 processor to access any PLB v46 peripherals placed on it while the slave bus allows other masters (on the slave PLB bus) to access MCI memory and the master PLB v46 bus. The PLB v46 supports dynamic bus sizing as well as programmable burst size.
MPLB
SPLB
PLB v46
PLB v46
e.g.
Memory
Controller
Hi-Speed
Peripheral GB
E-Net
UART
GPIO
Bus
Master
Off-Chip
Memory
Full system customization to meet performance, functionality, and cost goals
ZBT SSRAM
DDR SDRAM
SDRAM

9. IP Peripherals All are included FREE!
Bus infrastructure and bridge cores
Memory and memory controller cores
Debug
Peripherals
Arithmetic
Timers
Inter-processor communication
External peripheral controller
DMA controller
PCI
User core template
…and Other cores
Bus infrastructure and bridge cores
Fabric Co-processor Bus (FCB)
Fast Simplex Link (FSL)
DCR bridge and bus
PLB v46 to PLB v46 bridge
Local Memory Bus (LMB) (MicroBlaze processor)
Memory and memory controller cores
Block RAM (PLB v46/LMB)
PPC 440 DDR2 memory controller
Multi-port memory controller (SDRAM, DDR, DDR2)
Multi-channel external memory controller (SRAM, FLASH)
System ACE™ interface controller (Compact Flash)
Debug
ChipScope™ Pro tool (ILA, controller, PLB v46)
MicroBlaze Debug Module (MDM)
PPC JTAG controller
Peripherals
SPI interface, UART, UART lite
Hard-core tri-mode Ethernet MAC
10/100 Ethernet MAC

10. Lessons
Hardware Overview
PPC 440
Base System Builder
Summary

11. PowerPC 440 Processor Core
High performance
1,100+ DMIPS
29% faster per MHz than PPC 405 processor
Licensed IBM PPC 440 processor core
Industry standard
Superscalar
Multiple instructions per cycle
Uses PLB v46 CoreConnect bus architecture
Third-generation embedded processor core in the FPGA
The PowerPC 440 processor offers increased system performance compared to the Virtex-4 FX FPGA PowerPC 405 processor:
Improved DMIPS (1000+ vs. 700+)
2x the cache sizes (32K/32K vs. 16K/16K)
2x the PLB bandwidth (128 bit vs. 64 bit)
4x the APU bandwidth (128 bit vs. 32 bit)

12. Next Generation of Performance1
PowerPC 440 processor core
Highest performance FPGA embedded processor
Hardened processor interconnect
Simpler implementations
Simultaneous non-blocking access
Dedicated memory interface reduces bottlenecks
Enhanced APU
Supports double-precision FPU w/ key OSs
Custom hardware acceleration eliminates software bottlenecks
Full EDK support
Processor Block
DMA
DMA
SPLB0
PowerPC
440
MCI
APU
Control 2
Crossbar
MPLB
CPM
SPLB1
DMA
DCR
DMA 3 4
More than just a better processor!

13. PowerPC Processor – Basic Architecture
A 32-bit implementation of the PowerPC processor
64-bit operations are not supported
Processor does not implement floating point operations, although an FPU can be attached through the APU
Support for embedded system applications
Flexible memory management
Multiply and accumulate instructions for computationally intensive applications
Enhanced debug capabilities
64-bit time base
Fixed Interval Timer (FIT) and watchdog timer
Performance-enhancing features
Seven-stage highly pipelined
Single cycle multiply and multiply accumulate
Enhanced string and multiple word handling
Reduced branch latency using Branch Target Address Cache (BTAC)

14. Auxiliary Processing Unit (APU) Interface
Virtex-5 FXT devices
Coprocessor interface
Connects the PowerPC processor to fabric
Offload computations to fabric; hardware FPU, for example
Extends native PPC440 processor instruction set
Decodes but does not execute instructions
Tighter integration between processor and fabric
The PowerPC processor APU interface on Virtex-5 FPGAs enables the hardware accelerated co-processing mechanism to improve software and hardware co-design efficiency.
Integrating with XtremeDSP technology also opens the co-processing space for embedded computing in a fraction of the normal hardware development time.

15. Buses 101 Bus masters have the ability to initiate a bus transaction
Bus slaves can only respond to a request
Bus arbitration is a three-step process
A device requesting to become a bus master asserts a bus request signal
The arbiter continuously monitors the request and outputs an individual grant signal to each master according to the master’s priority scheme and the state of the other master requests at that time
The requesting master samples its grant line until granted access. When the current bus master releases the bus, the master then drives the address and control lines to initiate a data transaction to a slave bus agent.
Arbitration mechanisms
Fixed priority, round-robin, or hybrid
Arbitration can be hidden or non-hidden. Hidden arbitration indicates that another device will become the next master when the current master releases the bus. Non-hidden arbitration prevents another device from receiving a grant signal when the current master is driving the bus.

16. PPC 440 Processor Bus Example
PLBv46
ARB
DDR2
Memory
(off-chip)
SDRAM
PLBv46 Bus
Data: 128 bits
Address: 32 bits
Ethernet
To MPLB
MCI
Data: 128 bits
DDR2
Memory
Controller
MicroBlaze
UART
PLB v46: The PLB v46 interface supports a bus width up to 128 bits of data. The PPC 440 processor supports both a master and two slave PLB v46 buses. The PLB v46 supports dynamic bus sizing as well as programmable burst size.
The MPLB allows the PPC 440 processor or any master on the SPLB bus to be a master accessing devices on the MPLB bus (basically, the peripherals on the MPLB are the slaves that all the masters want access to). The SPLB does not allow the PPC 440 to access any of the peripherals on the SPLB. The SPLB allows its masters to access MCI-based memory and devices on the MPLB bus. The DMA master can also access MCI-based memory and devices on the MPLB bus.
MCI
GPIO
SPLB
MPLB
INTC
IIC
APU
Hi-Speed
PPC440
Mem Ctl
DMA
INTC
TEMAC
PLBv46
ARB
DMA
Data: 32 bits

17. PPC 440 Crossbar DMA MCI – Memory Controller Interface PLB master
Four channels – Up to four 32-bit channels (each direction)
Scatter/gather functionality
MCI – Memory Controller Interface
FIFO-like interface; no PLB required
Simplified interface: address, data, control
PLB master
Allows the PPC 440 processor to be a bus master
PLB slave – Up to two channels
Allows PLB slave access to main memory
APU – Coprocessor interface
The crossbar concept relieves the problem of busy buses. The PPC 440 processor crossbar is configured as a dual five-to-one multiplexer, meaning two independent and simultaneous connections between one of five masters to one of two slaves can happen at the same time.
Three of the five possible masters are the PPC 440 processor instruction read, data read, and data write buses. The other two possible masters are the outputs of two other multiplexers. These identical multiplexers further select between two DMA controllers and a PLB bus slave target. The two slave connections to the crossbar are a memory controller interface (MCI) to a DDRx RAM controller and a PLB bus master.

18. Crossbar DMA Controller
Multiple-channels – Up to four 32-bit channels (each direction)
Interface into PLB crossbar at 128-bit width
Peripheral interface
32-bit LocalLink
Independent transmit and receive
Asynchronous with the interconnect clock
Byte realignment on Tx and Rx
Efficient flow control management
Command translation
Scatter/gather functionality
Programmable by the processor or FPGA fabric
The PPC 440 processor also has four Direct Memory Access (DMA) ports. These are commonly used to connect to the tri-mode Ethernet MACs included with the Virtex-5 FPGA.

19. Memory Controller Interface
Enables direct connect of memory controller to processor
Increased performance
FIFO-like interface; no PLB required
Simplified interface: address, data, control
Performs row/bank detection
Reducing soft controller logic
Provides transaction pipelining
Up to eight read transactions from the crossbar
Data transaction support
32-, 64-, and 128-bit data transfer per cycle
Variable burst sizes
Each burst has its own address
Connect to Xilinx or a custom soft controller
The PPC 440 processor supports a Memory Controller Interface (MCI) port that is designed to connect directly to the DDR2 memory controller of the PPC processor. The separate memory interface improves system performance and enables access to larger memories.
DDR Memory Controller: The PowerPC 440 processor core has a non-bused, non-cacheable, low-latency data and instruction memory interface designed to connect with an external memory controller (DDR2 memory controller). One of the primary advantages of the MCI is that it guarantees a fixed latency of execution because there is no bus arbitration required.

20. Separate memory and I/O buses greatly improve system performance
Crossbar in Action
Performance
Processor Block
Crossbar
DMA
SPLB1
MCI
MPLB
DCR
APU
Control
CPM
PowerPC
440
SPLB0
External DDR2 Memory
PPC440MC DDR2
Memory Controller Interface
This is a typical embedded system: a PPC 440 processor, some DDR2 memory, and some peripherals.
Note that the peripherals are connected to the I/O or master PLB, while the memory is connected to the memory controller interface bus. Also note how the processor accesses the memory and peripherals through the crossbar.
All PowerPC 440 slave peripherals are placed on a PLB bus attached to the MPLB port. Likewise, any other master peripherals that need access to the MCI or MPLB bus peripherals would have to be attached to either the SPLB0 or SPLB1 slave PLB bus ports.
PLB V46
CAN
USB 2.0
System Monitor
GPIO
Separate memory and I/O buses greatly improve system performance

21. EDK Memory Controllers
Processor Block
Crossbar
DMA
SPLB1
MCI
MPLB
DCR
APU
Control
CPM
PowerPC
440
SPLB0
External DDR2 Memory
Memory Controller Interface
PPC440MC DDR2
Note that PowerPC 440 slave peripherals are connected to the master. These memory peripherals and the MCI memory will also be accessible to other masters that are connected to the SPLBx PLB port.
PLB V46
XPS_MCH _EMC
MPMC
XPS_ BRAM
XPS_MCH _EMC
MPMC
XPS_ System Ace
Flash
DDR
BRAM
SRAM
SDRAM
System
ACE

22. Crossbar in Action – TEMACs as Masters
Performance
Integration
TEMAC
Wrapper
Processor Block
DMA
DMA
External DDR2 Memory
PPC440MC DDR2
Memory Controller Interface
SPLB0
In this illustration, two embedded TEMACs have been added, attached to the two DMA channels in the upper peripheral block. Both TEMACs are potential masters to access the MCI or MPLB buses. Because they are both on the upper master, arbitration will be necessary to determine which of the TEMACs will be the master at any given time. The TEMACs are connected to the processor block through a thin wrapper that is provided with the embedded development tools and attached to the DMA port.
Note that this differs from the XPS_LL_TEMAC component, which is attached to the PLB bus. The XPS_LL_TEMAC component supports the hard TEMAC included with Virtex-4 and Virtex-5 FPGAs. The XPS_LL_TEMAC also supports the soft implementation for many FPGAs. Note that the soft version does have a charge associated with it; however, the hard versions are included for free with the silicon.
Adding the TEMACs this way is currently not supported with the BSB. To be completed, you will have to manually edit the design. Adding a TEMAC in the BSB will result in the TEMAC being attached to a PLB v46 bus.
For more information about the hard TEMAC, refer to the Virtex-4 Embedded Tri-Mode Ethernet MAC User Guide and the Virtex-5 Embedded Tri-Mode Ethernet MAC User Guide.
For more information about the soft tri-mode Ethernet MAC LogiCORE™ IP, refer to the LogiCORE Tri-Mode Ethernet MAC User Guide.
For more information about integrating the TEMACs with the PLB bus, refer to the product specifications (right-click the Local Link Tri-Mode Ethernet MAC in the IP Catalog).
PowerPC
440
MCI
APU
Control
Crossbar
MPLB
PLB V46
CAN
USB 2.0
System Monitor
GPIO
CPM
SPLB1
DMA
DCR
DMA
Four built-in DMA channels provide high-speed access to memory or I/O

23. PowerPC 440 Processor Crossbar in Action
Performance
Integration
Flexibility
TEMAC
Wrapper
TEMAC
Wrapper
Processor Block
DMA
DMA
External DDR2 Memory
PPC440MC DDR2
Memory Controller Interface
SPLB0
All Xilinx processor systems have standardized on the PLB v46. In addition, you can have as many MicroBlaze processors in an FPGA as will fit.
In this example, a MicroBlaze processor system is attached to a PPC processor via a PLB bus. This allows the MicroBlaze processor core to access any peripherals attached to the PPC processor’s slave bus (which is the MPLB port) and memory on the MCI. But the PPC cannot gain access to any of peripherals attached to the SPLB port because this connection cannot be made by the crossbar. This is a simple multiprocessing system.
This example just illustrates the use of the SPLB interface, showing that it allows “multi-ported” access to the memory and I/O of the PPC 440 processor block.
PowerPC
440
MCI
APU
Control
Crossbar
MPLB
PLB V46
CAN
USB 2.0
System Monitor
GPIO
CPM
SPLB1
I2C
GPIO
Timer
Memory Controller
RS232
Custom IP
DMA
DCR
DMA
PLB V46
External masters can access memory or I/O through crossbar’s SPLB

24. Lessons
Hardware Overview
PPC 440
Base System Builder
Summary

25. Starting out with a Processor Design
Many vendors support evaluation and demo boards with Xilinx FPGAs
Xilinx
Avnet
Digilent
Base System Builder (BSB) is a wizard to facilitate a fast processor-based system design by high abstraction, level-specification entry
Virtex®-5 FPGA ML507
Spartan®-6 SP605 FPGA
Spartan-3E FPGA 1600E

26. Create a New Project Using the BSB
BSB enables fast design construction
Creates a completed platform and test application that is ready to download
Creates this system faster than you could by editing the MHS directly
Automatically matches the pinout of the design to the board
The Set Project Peripheral Repository option is used for storing custom peripherals and drivers in a reserved location
The first lab, “Hardware Construction with the Base System Builder,” will use the BSB.
The peripheral repository is a place to store custom bus peripherals; the default location is the current project.

27. Selecting a Board
Xilinx and its distribution partners sell demo boards with a wide range of added components
This dialog box allows you to quickly learn more about all available demo boards
It also allows you to install the necessary BSB files if you want to target a demo from another vendor
Note that you can also create your own BSB file for a custom board
Stepping is a means of providing the most currently available architectural resources as soon as it becomes available.
Each device, once available, has a mark that specifies what step device is being used.
Enter the value placed on the package into the software if the device is early access silicon.

28. Selecting a Processor
Base System Builder supports a single- or dual-processor system
When selecting the multi-processor option, later screens will have choices of processors to attach peripheral components and various inter-processor communication schemes.

29. Configuring the Processor
Processor clock frequency is the clock rate connected directly to the processor
Bus clock frequency is the clock rate of all bus peripherals in the system
These selections will automatically customize the clock generator module
The appropriate debug interface is added automatically
The selections made here will instantiate and configure the system clocking component.
The debug interface is always included. For the MicroBlaze processor, a MDM debug peripheral will be included and hooked to the FPGA internal BSCAN component for visibility on the FPGA JTAG pins.
For the PowerPC® processor, which has the debug module in silicon, a choice is given to hook the internal JTAG signals from the PPC to either FPGA pins or the BSCAN module.

30. Configuring the I/O Interfaces
Choose the peripherals you need from those available for your demo board
Peripherals can be added or removed
Most peripherals are customizable via drop-down lists when selected
Most peripherals support the use of interrupts
Internal peripherals exist for all board hardware configurations
The Base System Builder (BSB) determines and lists what external memory and peripheral devices are available for your development board. You can enable or disable each interface by adding or removing from the list of available devices to the processor list.
The following are commonly used devices:
Serial devices: Universal Asynchronous Receiver-Transmitter (UART), IIC, and Serial Peripheral Interface (SPI)
General-purpose I/O devices: Light Emitting Diodes (LEDs), dip switches, and pushbuttons
External memories: Synchronous Dynamic RAM (SDRAM), Double Data Rate (DDR), and Static RAM (SRAM)
High-speed communication devices: Ethernet

31. A Good Start on a Processor Design
Basic PowerPC processor system
Basic MicroBlaze processor system

32. Lessons
Hardware Overview
PPC 440
Base System Builder
Summary

33. Summary
The PPC 440 processor crossbar switch speeds system performance utilizing an alternative architecture (to bus) that is 128-bit wide
The crossbar clock is usually the fastest in the embedded system
All other embedded clocks are relative to the crossbar clock (bus, memory, DMA)
The PPC 440 processor supports the attachment of one master PLB bus (for connection to slave peripherals) and two slave PLB buses (for connection to other system master components)
The PPC 440 processor has a Memory Controller Interface (MCI)
Allows the fastest memory access possible by connecting to a Xilinx memory controller
The PPC 440 processor has four DMA controller ports
The PPC 440 APU supports co-processors built in FPGA fabric

34. Where Can I Learn More? Xilinx Embedded Processing page
Learn more about Embedded Design Kits for all of our device families
Xilinx online documents
Getting Started with the Embedded Development Kit
Processor IP Reference Guide
Right-click any peripheral from the IP Catalog to learn more about it
Embedded Systems Tools Guide
Xilinx Drivers
Processor reference guides
PowerPC 405/440 Processor Block Reference Guide
MicroBlaze Processor Reference Guide
For all docs, select Help  EDK Online Documentation from the EDK tools

35. Where Can I Learn More? Xilinx Training Courses
Embedded Systems Development course
Rapidly architect an embedded system
Introduction to most of the EDK tools
Embedded Systems Software Development course
Rapidly architect an embedded software system
Introduction to the SDK (Software Development Kit)
Advanced Embedded Systems Development course
Take advantage of advanced features of the PPC440
Apply advanced debugging techniques including ChipScope
Design a Flash memory-based system and boot load from off-chip Flash memory
Customers spend 50% of their time in lab

36. What’s Next? Related Video Courses
Embedded Design with the MicorBlaze Soft Processor Core
Embedded Design with the Xilinx Embedded Developers Kit

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