1. DAC Interfacing V ref CPU D Q DAC D Q V out Clock Address bus Address
decoder
IOW
AEN

2. IBM – PC Ports MEMR R/W MEMW IO/M IOR DEN IOW DEN ALE Address bus
Data bus
MEMR
MEMW
IOR
IOW
R/W
IO/M
DEN
DEN
ALE
OUT DX,AL
OUT DX,AX
Address bus
300H - 31FH For prototype Cards
AEN=0 For I/ O ports A A5 A A A0
AEN=1 For DMA For Card For Port For Byte
Selection Selection Selection

3. Address Decoder IN 300H decoder IN 302H decoder IN 304H OUT 300H
300 – 31 FH
decoder
IOR
decoder A1 A2 A3 A4
IN H A5 A6 A7
IN H
IN H A1 A2 A3 A4
OUT H
OUT H
OUT H A9 A8
AEN
IOW

4. Mov Cx, count * OUT Dx, AL Mov AL, SI INC SI ”LODSB“ “OUT DX,AX” Or
For 10- bit
or bit
DAC Or
“LODSW”
DEC CX
JNZ *
” * LOOP“
Mov BL , M
**DEC BL
JNZ **
Delay to adjust “ Ts”

5. 10 – bit
DAC D1 D0 D2 D7 A0 CE
OUT 300H
V out

6. V ref
ADC
VIN
CPU
data
bus
Start
IN 300H
END DO
OUT 302H
IN 302H

7. ** OUT 302H, AL * IN AL, 302 H AND AL, 1 JNZ * IN AL, 300H STOSB
LOOP **
Delay to adjust Ts

8. CPU Start End interrupt V cc INTR End Int. service routin OUT 304H, AL
D Q
Elk
clr
End
Int. service routin
OUT 304H, AL
IN AL, 300H
STOSB
OUT 302H, AL
IRET
Out 304 H

9. ADC 10-bit IN AX, 300H STOSW V in OE IN 300H B0 B1 D0 D1 B7 B0 B1 D7