1. Examples of Basic Combinational
Logic Circuit Design
Teacher：Wang-xiu min
Office: 514
Telephone:

2. Combinational Circuit Design
Combinational circuits
inputs
outputs
Examples:
-- gate circuit
-- multiplexer
--decoder
--priority encoder
--adder
Outputs are functions of inputs in combinational
logic circuits.

3. input [3:0] a,b ; // port declarations input ci ;
Example: 4-bit adder
module add4 (s,c3,ci,a,b)
input [3:0] a,b ; // port declarations
input ci ;
output [3:0] s : // vector
output c3 ;
wire [2:0] co ;
add a0 (co[0], s[0], a[0], b[0], ci) ;
add a1 (co[1], s[1], a[1], b[1], co[0]) ;
add a2 (co[2], s[2], a[2], b[2], co[1]) ;
add a3 (c3, s[3], a[3], b[3], co[2]) ;
endmodule a0 a1 a2 a3 c3 ci

4. behavioral statements of Veriolg HDL
------case
E.g. 4-to-1 mux:
module mux4_1(out, in, sel);
output out;
input [3:0] in;
input [1:0] sel;
reg out;
wire [3:0] in;
wire [1:0] sel;
or sel)
case (sel)
0: out = in[0];
1: out = in[1];
2: out = in[2];
3: out = in[3];
endcase
endmodule
case (expression)
alternative1: statement;
alternative2: statement; .
alternativej: statement;
[default: statement;]
endcase

5. behavioral statements of Veriolg HDL
------for
for (init_assignment; cond; step_assignment)
stmt;
module count(Y, start);
output [3:0] Y;
input start;
reg [3:0] Y;
wire start;
integer i;
initial
Y = 0;
start)
for (i = 0; i < 3; i = i + 1)
#10 Y = Y + 1;
endmodule

6. Decoder 2to4 always @(w or en) for (k= 0; k< =3; k = k + 1)
if((w==k)&&(en=1))
Y[k]=1;
Else
Y[k]=0;
endmodule
module dec2to4(W,Y, en);
output [3:0] Y;
input en;
Input [1:0] w;
reg [3:0] Y;
Integer k;

7. Decoder Example: 3-to 8 decoder with an case statement
module decoder3_8(Y,A);
input[2:0] A;
output[7:0] Y;
reg[7:0] Y;
begin
case(A)
3'd0:Y=8'b ;
3'd1:Y=8'b ;
3'd2:Y=8'b ;
3'd3:Y=8'b ;
3'd4:Y=8'b ;
3'd5:Y=8'b ;
3'd6:Y=8'b ;
3'd7:Y=8'b ;
endcase
end
endmodule

8. Decoder module decoder(o,enb_,sel) ;
Example: 3-to 8 decoder with an enable control
module decoder(o,enb_,sel) ;
output [7:0] o ;
input enb_ ;
input [2:0] sel ;
reg [7:0] o ;
(enb_ or sel)
if(enb_)
o = 8'b1111_1111 ;
else
case(sel)
3'b000 : o = 8'b1111_1110 ;
3'b001 : o = 8'b1111_1101 ;
3'b010 : o = 8'b1111_1011 ;
3'b011 : o = 8'b1111_0111 ;
3'b100 : o = 8'b1110_1111 ;
3'b101 : o = 8'b1101_1111 ;
3'b110 : o = 8'b1011_1111 ;
3'b111 : o = 8'b0111_1111 ;
default : o = 8'bx ;
endcase
endmodule

9. Decoder Example: 3-to 8 decoder with an input control
3’d0: out=8’b ;
3’d1: out=8’b ;
3’d2: out=8’b ;
3’d3: out=8’b ;
3’d4: out=8’b ;
3’d5: out=8’b ;
3’d6: out=8’b ;
3’d7: out=8’b ;
endcase
end
endmodule
module decoder_38(out,in);
output[7:0] out;
input[2:0] in;
reg[7:0] out;
(in)
begin
case(in)

10. Priority encoder Example: Priority encoder with a input control
4’b1ⅹⅹⅹ: y=3;
4’b01ⅹⅹ: y=2;
4’b001ⅹ: y=1;
4’b0001: y=0;
default:begin
z=0;y=2’bx;
end
endcase
endmodule
module priority(y,in);
output[1:0] in;
Output z;
input[3:0] in;
reg[1:0] y;
Reg z;
(in)
begin
Z=1;
casex(in)

11. Priority Encoder always @ (d0 or d1 or d2 or d3) if (d3 == 1)
{x,y,v} = 3’b111 ;
else if (d2 == 1)
{x,y,v} = 3’b101 ;
else if (d1 == 1)
{x,y,v} = 3’b011 ;
else if (d0 == 1)
{x,y,v} = 3’b001 ;
else
{x,y,v} = 3’bxx0 ;

12. Priority encoder8-3 module pencoder8_3(din,dout); input[7:0] din;
output[2:0] dout;
function[2:0] code;
if(din[7]) code=3'd7;
else if(din[6]) code=3'd6;
else if(din[5]) code=3'd5;
else if(din[4]) code=3'd4;
else if(din[3]) code=3'd3;
else if(din[2]) code=3'd2;
else if(din[1]) code=3'd1;
else code=3'd0;
endfunction
assign dout=code(din);
endmodule

13. Parity Checker Example: A parity check bit generator. reg partial;
integer n;
partial = data[0];
for ( n = 0; n <= 7; n = n + 1)
begin
partial = partial ^ data[n];
end
parity <= partial;
endmodule
module parity_chk(data, parity);
input [0:7] data;
output parity;
reg parity;
(data)
begin: check_parity

14. Example: A parity check bit generator.
module parity(even_bit,odd_bit,input_bus);
output even_bit,odd_bit;
input[7:0] input_bus;
assign odd_bit=^input_bus;
assign even_bit=~odd_bit;
endmodule

15. Multiplexor module mux2_1 (out,a,b,sel) ; output out ; input a,b,sel ;
not (sel_, sel) ;
and (a1, a, sel_) ;
and (b1, b, sel) ;
or (out, a1, b1) ;
endmodule
Net-list
(gate-level)

16. Multiplexor 4-to-1 multiplexor
module mux4_1 (out, in0, in1, in2, in3, sel) ;
output out ;
input in0,in1,in2,in3 ;
input [1:0] sel ;
assign out = (sel == 2'b00) ? in0 :
(sel == 2'b01) ? in1 :
(sel == 2'b10) ? in2 :
(sel == 2'b11) ? in3 :
1'bx ;
endmodule

17. Multiplexor module mux4_1 (out, in, sel) ; output out ;
input [3:0] in ;
input [1:0] sel ;
reg out ;
or in) begin
case(sel)
2’d0: out = in[0] ;
2’d1: out = in[1] ;
2’d2: out = in[2] ;
2’d3: out = in[3] ;
default: 1’bx ;
endcase
end
endmodule
out = in[sel] ;

18. Multiplexor Example: A 4-1 mux with if-else sentence.
module mux4_1(out,in0,in1,in2,in3,sel);
output out;
input in0,in1,in2,in3;
input[1:0] sel;
reg out;
or in1 or in2 or in3 or sel)
begin
if(sel==2'b00) out=in0;
else if(sel==2'b01) out=in1;
else if(sel==2'b10) out=in2;
else out=in3;
end
endmodule

19. Multiplexor Example: A 4-1 mux with case sentence.
module mux4_1(out,in0,in1,in2,in3,sel);
output out;
input in0,in1,in2,in3;
input[1:0] sel;
reg out;
or in1 or in2 or in3 or sel)
begin
case(sel)
2'b00: out=in0;
2'b01: out=in1;
2'b10: out=in2;
default: out=in3;
endcase
end
endmodule

20. ROM Example: A ROM realized by combinational circuit.
module rom(addr,data);
input[3:0] addr;
output[7:0] data;
function[7:0] romout;
case(addr)
0: romout=0;
1: romout=1;
2: romout=4;
3: romout=9;
4: romout=16;
5: romout=25;
6: romout=36;
7: romout=49;
8: romout=64;
9: romout=81;
10: romout=100;
11: romout=121;
12: romout=144;
13: romout=169;
14: romout=196;
15: romout=225;
default: romout=8’hxx;
endcase
endfunction
assign data=romout(addr);
endmodule

22. Summary
In this chapter, we discussed the following aspects of Verilog:
case (expression)
alternative1: statement;
alternative2: statement; .
alternativej: statement;
[default: statement;]
endcase
for (init_assignment; cond; step_assignment)
stmt;
Priority Encoder\3-to 8 decoder