1. EEE2135 Digital Logic Design Chapter 6
EEE2135 Digital Logic Design Chapter 6. Latches/Flip-Flops, Registers/Counters, Sequential Circuits
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2. 1. Delay and Latches Signal Storage Delays
as voltage level – static memory
as charges – dynamic memory
Delays
due to gates and interconnection lines
Uncertain delays :
typical (nominal), min/max delays
Statistical delay
Rising/falling delay: 10%→90%, 90%→10% of voltage swing
Transport delay : port- to-port (pin-to-pin) delay
Inertial delay
Tends to block narrow pulses (inertia, resistance to change)
Energy to charge/discharge internal capacitances
Unbalance between rising & falling delays

3. Latches Closed signal path : feedback loop
Stability and Meta-stability
Unstable
Leads to oscillation
Meta-stable
Temporarily stuck between 0 and 1
Responsible for rare and hard-to-find failure
Bistable
Two stable states A B

4. It is sensitive to noise
SR Latches
Structure
Behavior
Unpredictable behavior : depends on propagation delay of NORs/NANDs – forbidden input conditions
It is sensitive to noise
To alleviate the noise problems, a control signal is used - Gated SR latch
iii. Level-sensitive & Asynchronous – hard to control
S R
0 0
0 1
1 0
1 1 *X 1
S R
0 0
0 1
1 0
1 1 1 *X S R Q
Forbidden inputs in
RS latch with NANDs/NORs

5. d. Gated SR latch - It can be usable SR latch
Improvement of SR-latch (Gated SR-latch)
Controlled by a control signal
Still level-sensitive (w.r.t. control signal)
Short duty cycle to prevent errors
d. Gated SR latch - It can be usable SR latch S R
Control Q
Still, problem with SR latch –
Noise-sensitivity and forbidden input conditions

6. Latch Applications
as a temporary storage element needed for data processing and I/O circuits without complex feedback
to reduce glitches
RS latch has forbidden input condition
- D latch

7. 2. Clocks and Flip-flops Basic Concepts Clocking Methods
More reliable storage elements in more general sequential circuits
F/F: a bistable memory with precise timing control (by clock)
Clocking Methods
Level-sensitive : latches
Positive (negative) edge-triggered
* F/Fs use the clock edge for the output change

8. A negative edge-triggered SR flip-flop (a simple circuit)Q Q R
Clock

9. 3) A positive-edge-triggered D flip-flop
1. P1 = P2 = 1 and P3 = D, p4 = D’ when Clock = 0
2. P1 = D’ P2 = D when Clock goes to high
3. Further changes in D do not affect Q when Clock = 1
if D = 0 at then P2 = 0 -> P4 = 1 regardless of D
if D = 1 at then P1 = 0 -> P2 = P3 = 1 regardless of D
P3, P4 must be stable when Clock goes to high :
Setup time is delay from D through gate 4 to gates 1 and 3 D
Clock P4 P3 P1 P2 5 6 1 2 3
(a) Circuit Q
(b) Graphical Symbol (c) Transition Table 4
Q(n+1) = D(n)
D(n)
Q(n+1) 1

10. Reset(Clear) and Preset: Asynchronous inputs
Master-slave D flip-flop
Both clocking edges Q D
Clock
(a) Circuit
Preset
Clear
Reset(Clear) and Preset: Asynchronous inputs

11. JK Flip-flop Structure b. Transition Table
- Next page
Transition-map for Q(n+1) d. Excitation table
(for deriving transition function)
J(n) K(n)
Q(n+1)
Q(n) 1
Q(n)’
Q(n)
J(n) K(n)
Q(n)→Q(n+1)
J(n)K(n) S(n)R(n) D(n)
0 x x
1 x x
x x

12. JK flip-flop (a) Circuit Q(n+1) = J(n)Q(n)’ + K(n)’Q(n) : JK F/FD Q Q K Q Q
Clock
(a) Circuit J Q K
Q(n+1) = J(n)Q(n)’ + K(n)’Q(n) : JK F/F
Q(n+1) = S(n)R(n)’ + R(n)’Q(n) : SR F/F
Q(n+1) = D(n) : D F/F
(b) Transition functions
(c) Graphical symbol

13. T flip-flop D Q T
Clock D Q T
Clock

14. 3. Flip-flop Behavior 1) States 2) State Behavior
Internal state and total state (the set of stored data )
State transition table and diagram
Defines a memory’s(State Register) next state function
Allows repetitive behavior to be easily visualized
2) State Behavior
Flip-flop behavior described by means of state table/diagram
Each transition is triggered by clock signal
Described by characteristic equation
JK flip-flop 1
(0, 0)
(0, 1)
Set
Reset
(1, 0)
(1, 1)

15. 3) Registers A set of flip-flops with common control logic
Parallel-load type, shift-type, shift with parallel-load
A simple shift register D Q
Clock In
Out t 1 2 3 4 5 6 7 =
(b) A sample sequence
(a) Circuit

16. d. Parallel-load shift registerQ 3 2 1
Clock
Parallel input
Parallel output
Shift/Load
Serial
input D

17. 4) Counters Asynchronous (Ripple) Counter
A cascade of flip-flops, each of which toggling its successor
Slow, lack of generality in design process
Synchronous Counter
Popular
Uses a common clock for all f/f’s
Ring Counter
Rotates a single 1 thru all its flip-flops
State diagram 0001→0010→0100→1000 →0001
Decoder is embedded
Johnson Counter
Similar to ring counter
State diagram
0000→0001→0011→0111→1111→1110→1100→1000 →0000
Only one bit change between adjacent states – no glitches

18. Asynchronous Counter (a) Circuit (b) Timing diagram T Q Clock 1 Count2
(a) Circuit
Count 3 4 5 6 7
(b) Timing diagram

19. Synchronous Counter (a) Circuit (b) Timing diagram T Q Clock 1 Count 32
(a) Circuit
Count 3 5 9 12 14
(b) Timing diagram 4 6 8 7 10 11 13 15

20. Ring Counter Q Q Q 1 n – 1
PR’ D Q D Q D Q Q Q Q R’ R’ R’
Reset
Clock

21. Johnson Counter D Q
Clock 1 n –
Reset R’ R’ R’

22. F/F Timing Inputs to f/f stabilized f/f outputs stabilized
tSU
Clk D Q
tff
tCC
tSU th
Inputs to f/f stabilized
f/f outputs stabilized
tP, clk > tSU + tff + tCC + margin
fclk < 1/(tSU + tff + tCC + margin)

23. 4. Memory
An SRAM cell
Sel
Data
An DRAM cell
Sel
Data

24. A 2m x n SRAM block Data inputs d d d Write Sel Sel a Sel decoder a– 1 n – 2
Write
Sel
Sel 1 a
Sel 2
decoder a 1
Address m
-to-2 a m – 1 m
Sel 2 m ” 1
Read
Data outputs q q q n – 1 n – 2

25. 4. Model of Sequential Circuits
Sequential vs. Combinational Circuits
Sequential circuits: Outputs depend on both the current inputs and present state determined by the past input history
State register required to record the past inputs
Sequential Circuit Structure
Moore Model POs independent of PIs, depend on PS
Mealy Model POs depend on PIs and PS
State Behavior
State (Transition) Table
Behavioral description of a sequential circuit requires to list all possible input/output sequences (tt impractical)
State table to represent the behavior of a sequential circuit ex. State table of a serial adder
State (Transition) Diagram
Representation of a state table in graphical form
Vertex : state, Arc : state transition, Label : x/z (inputs/outputs)
Reset signal to represent the initial state

26. 5. Analysis of a Sequential Circuit
Analysis Procedure
Derive Boolean equations from logics at each input of FFs
Construct transition table
State table can be obtained by replacing the bit patterns by symbols
Circuit behavior can be known
Behavior Extraction
Combinational function identification
State/State transition identification
Formal behavioral specification

27. 6. Timing control and clock
Clocks
Inputs/outputs can change at any time w/o clocking
to determine precisely when states change and
to minimize sensitivities to glitches
to control the overall operations
Delays in sequential circuits
Propagation delay
Longest path constraint
Shortest path constraint
- logic signals travel too fast around main feedback loop
Clock signal design
Clock skew
Clock signal spreads over system – different delays for different clock signals applied to f/f’s
Max. allowed clock skew – max. time difference which can occur between almost – simultaneous click transitions which f/f’s will treat as being simultaneous

28. F/F Timing Inputs to f/f stabilized f/f outputs stabilized tSU tSU th
Clk D Q
tff
tCC
tSU th
Inputs to f/f stabilized
f/f outputs stabilized
tP, clk > tSU + tff + tCC + margin (15~25%)
fclk < 1/(tSU + tff + tCC + margin (15~25%))

29. 7. Sequential Circuit Synthesis
Design Process
State behavior specification
Construct state diagram which precisely captures i/o behavior
Internal states and transitions are identified
State assignment : NP, heuristic algorithms required ex. NOVA (UCBerkeley), Albatross
Construct transition table and excitation table
Derive NS equations and output equations
Logic design for each FF Input
Detailed Design Process
Problem specification : sometimes informal
Defining state behavior & improving it
State assignment
Combinational function spec. & circuit design
Design verification
- Simulation is essential for verifying the correctness of designs

30. State diagram of a simple sequential circuit
Example Design of a Sequential Circuit
State diagram of a simple sequential circuit
State-assigned table C z 1 =
Reset B A w
Present
Next state
state w = 1
Output y 2 Y z A 00 01 B 10 C 11 dd d

31. Derivation of Logic Expressionsy w 00 01 11 10 1 2 Y wy = d + z ( )
Ignoring don't cares
Using don't cares

32. Final implementation