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Circuit diagram for interfacing Common Anode 7-Segment Display.

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Presentation on theme: "Circuit diagram for interfacing Common Anode 7-Segment Display."— Presentation transcript:

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9 Circuit diagram for interfacing Common Anode 7-Segment Display

10 Circuit diagram for Common Cathode 7-Segment Display

11 Interface an 8-digit 7 segment LED display using 8255
In this circuit port A and port B are used as simple latched output ports. Port A provides the segment data inputs to the display and port B provides a means of selecting a display position at a time for multiplexing the displays. A0-A7 lines are used to decode the addresses for 8255.

12 The Light Emitting Diode (LED), finds its place in many applications in this modern electronic fields. One of them is the Seven Segment Display. Seven-segment displays contains the arrangement of the LEDs in “Eight” (8) passion, and a Dot (.) with a common electrode, lead (Anode or Cathode). The purpose of arranging it in that passion is that we can make any number out of that by switching ON and OFF the particular LED’s. Here is the block diagram of the Seven Segment LED arrangement.

13 LED’s are basically of two types:
Common Cathode (CC) All the 8 anode legs uses only one cathode, which is common. Common Anode (CA) The common leg for all the cathode is of Anode type. For the discussion purpose, we use CC LED, where by just reversing the logical voltages we can implement the same for CA LED also. In a CC LED, all the 8 legs (‘a’ through ‘h’) are of anode type and the common cathode will be connected to the GND of the supply. By energizing any of the legs with +5 Volts will lead to switch the correspondent segment ON. In the microprocessor binary system, 0Volts will be considered as Binary 0, and 5Volts will be considered as Binary1. Considering these two condition, we can make an arrangement as the microcontroller gives OUT the 0s and 1s through its ports, which is connected to the 8 legs of the LED. Of course, we can control the Port Output; implicitly we can Switch-ON required legs of the display. There 2 methods of interfacing LED with the Microcontroller Intel 8051/8951. Using lookup table. This uses 7 output pins of microcontroller Using 7447 decoder. This method uses 4 output pins of microcontroller The difference between the two main methods is simple and clear. In both the cases, microcontroller communicates with external world through its ports. But, in the 1st case, we connect all the 8 pins of the port directly to the LED and control the voltage through the ports manually to display the desired number. But, in the second case, we send the BCD of the number that we wanted to display to a middleware IC 7447, the BCD to LED code converter, which by itself gives out the correspondent 7 segment codes to the LED. Here we explain using lookup table. Click here for the method “using 7447 decoder” Using 7447 decoder: The IC7447 is a BCD to 7-segment pattern converter. This setup is the advanced form of the <previous> setup where we entered the patterns manually to display the desired character. Here in this case, the IC7447 takes the Binary Coded Decimal (BCD) as the input and outputs the relevant 7 segment code. We connect first four pins of the microcontroller Port 2  to the 7447 and the Output 8 pins of 7447 to the 8 legs of the LED as shown in the figure. Te circuit diagrams are shown below, the first figure is interfacing the CA LED where as the second is of CC LED. The number required to display is sent as the lower nibble of the Port 2 of the Microcontroller. The 7447 converts the four input bits (BCD) to their corresponding 7-segment codes. The outputs of the 7447 are connected to the 7-segment display.

14 Static display

15 Dynamic display

16 For 8255, port A and B are used as output ports
For 8255, port A and B are used as output ports. The control word format of 8255 according to hardware connections is

17 HDD Organization Arm Assembly Spindle Cylinder Head Arm Platter Track

18 8272 - FLOPPY DISK CONTROLLER
The 8272 is a LSI Floppy Disk Controller (FDC) Chip, which contains the curcuitry and control functions for interfacing a processor to 4 Floppy Disk Drives. It is capable of supporting either IBM 3740 single density format (FM), or IBM System 34 Double Density format (MFM) including double sided recording. The 8272 provides control signals which simplify the design of an external phase locked loop, and write precompensation circuitry. The FDC simplifies and handles most of the burdens associated with implementing a Floppy Disk Drive Interface.

19 8272 - FLOPPY DISK CONTROLLER

20 FDC IC FDC SYSTEM INTERFACE FDD interface circuits
62 P I N E D G C O T R DS0 AEN FDD interface circuits DS1 A0 – A9 MOTOR ON 0 IOW# MOTOR ON 1 IOR# HEAD SELECT D0 – D7 DIRECTION FDC IC STEP DRQ2 WRITE ENABLE DACK2# WRITE DATA T/C READ DATA IRQ6 INDEX System Interface Circuits TRACK 0 RESET DRV WRITE PROTECT System Interface DISKETTE CHANGE Device Interface

21 Overall operation of Floppy Disk Subsystem
In the PC , operations related to the FDD are done by coordination between various s/w & h/w modules: BIOS routines, DOS, application programs or user command to DOS, DMA controller, FDC & FDD

22 Floppy Disk Drive Functions
Loading r/w heads Moving the r/w heads by one track for every STEP pulse. The DIRECTION signal decides the direction of head movement. Writing data on disk when WRITE ENABLE signal is active. Rotating the disk when MOTOR ON signal is active. Responding to the signals from controller when DRIVE SELECT is Active. Presenting the o/ps to Index sensor, Write protect sensor, Track 0 sensor etc. when DRIVE SELECT is Active.

23 FDC Functions Analyzing the commands received from CPU, executing the commands & building up various status parameters. Receiving data byte from system data bus, serializing the data byte it into bit stream, adding clock bits with data bits as per the MFM format. Separating clock bits & data bits, de-seriazing the data bits into data bytes & presenting them to the system Generating CRCC while writing on the disk. Recalculating CRCC while reading & verifying it. Locating the desired sector by matching sector ID with desired sector no. Maintaining the current track no. Determining the desired direction of head movement Calculating the diff. Between the current track no. & desired track no. & issuing corresponding no. Of STEP pulses to the FDD Maintaining the status of the FDD

24 The following commands are available
Read data Write Deleted data Read ID Read deleted data Write deleted data Read A track Seek Scan equal Recalibrate Scan high or equal Sense interrupt status Scan low or equal Sense drive status Specify Format A track

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26 Sequence controller/Timing state logic
Sector buffer addressing & control Sector buffer RAM ADDRESS BUFFERS System Command Processor Device interface Circuits Port address decoder Data serializer Write precompensation HDC BIOS ROM DATA BUFFERS Data deserializer Data seperator ECC generation&checking logic Reset & Control

27 BLOCK COUNT OR INTERLEAVE
DEVICE CONTROL BLOCK BYTE 7 6 5 4 3 2 1 OPCODE d HEAD NUMBER CYN MSB SECTOR NUMBER CYLINDER NUMBER LSB BLOCK COUNT OR INTERLEAVE R1 R2 SP

28 HDC COMMANDS Test drive ready Recalibrate Request Sense status
Format Drive Read Verify Format Track Format bad track Read Write Seek Initialize Drive parameters

29 HDC COMMANDS Read ECC burst Error length Read Sector buffer data
Write Sector buffer RAM diagnostics Drive Diagnostics Controller internal diagnostics Read long Write long


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