1. Winter 2017 S. Areibi School of Engineering University of Guelph
ENG3380 Computer Organization and Architecture “Micro Programmed Control: Introduction”
Winter 2017
S. Areibi
School of Engineering
University of Guelph

2. Topics Design of Control Units Hardwired Control Units
One Flip Flop per State
Sequence Register and Decoder
Multiplier Example
Programmable Control Units
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3. References
“Computer Organization and Architecture: Designing for Performance”, 10th edition, by William Stalling, Pearson.
“Computer Organization and Design: The Hardware/Software Interface”, 4th edition, by D. Patterson and J. Hennessy, Morgan Kaufmann
Computer Organization and Architecture: Themes and Variations”, 2014, by Alan Clements, CENGAGE Learning
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4. Introduction

5. Parts of CPUs Datapath Control unit
The registers and logic to perform operations on them
Control unit
Generates signals to control datapath
Control
Data Path

6. The Control Unit
The binary information stored in a digital computer can be classified as either data or control information.
Data is manipulated in a data-path
To perform arithmetic, logic, shifting, and other data-processing tasks.
These operations are implemented with ALUs, registers, multiplexers, and busses.
The control unit
Provides signals that activate the various micro-operations in the data-path to perform the specified data processing tasks.
The control unit also determines the sequence in which the various actions are performed (i.e. when they are to be performed)

7. Control Unit Types Two distinct classes: Hardwired Programmable
A hardwired Control does not fetch instructions from a memory but  just determines the operations to be performed and the sequence of those operations based only on inputs and status bits.
A programmable control unit has:
An external ROM or RAM array for storing instructions and control information
A program counter (PC) or other sequencing register with contents that points to the next instruction to be executed
Decision logic for determining the sequence of operations and logic to interpret the instructions

8. Hardwired Control Designing the Control Unit:
Use a finite State Machine “FSM” (Moore or Mealy) and implement using D-FF or JK-FF (gets ugly as states increase!!)
Start with an FSM and then:
One Flip-flop per State: A flip-flop is assigned to each of the states and at any time, only one of the flip flops contains a 1, with all the rest containing 0.
Sequence Register and Decoder Uses a sequence register for the control states and a decoder to provide an output signal corresponding to each of the states.

9. I. One Flip-Flop per State
As the name implies the method uses one flip-flop per state and a simple set of transformation rules to implement the circuit.
The design starts with the ASM chart,
Then all you do is replace:
A State Box with a D flip-flop,
A Scalar Decision Box with a demultiplexer with 2 outputs,
A Vector Decision Box with a (partial) demultiplexer
Any Junction with an OR gate, and
Any Conditional Output with an AND gate (for a Mealy Machine!!)

10. Sequence Register and Decoder
This method uses a decoder and a set of flip flops (or a register) to implement the circuit.
The design starts with the ASM chart,
According to the number of states 2n, we will use n flip flops (log2 # state)
Construct State Table (directly from ASM)
Use an n-to-2n decoder  has 2n outputs

11. Problems With HardWired Designs
Sequencing & micro-operation logic gets complex
Difficult to design, prototype, and test
Resultant design is inflexible, and difficult to build upon
(Pipeline, multiple computation units, etc.)
Adding new instructions requires major design and adds complexity quickly

12. Micro-programmed Control
Use sequences of instructions to control complex operations
An alternative to a hardwired control unit
Called micro-programming, microcode, or firmware

13. Microprogrammed
Control

14. Micro-Programmed Control
A control unit with its binary control values stored as words in memory is called a micro-programmed control.
Each word in the control memory contains a microinstruction that specifies one or more micro-operations for the system.
A sequence of microinstructions constitutes a microprogram.
A micro-program is often fixed at the time of the system design and so is usually stored in ROM.
A micro-program can also be written in RAM but has to be loaded initially at system startup.
microinstruction
microprogram
Memory

15. ASM Chart  Microprogrammed Control
microinstruction
microprogram
Memory
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16. Microprogrammed Control Organization
Control Memory
»A memory is part of a control unit :
»Computer Memory (employs a microprogrammed control unit)
Main Memory : for storing user program (Machine instruction/data)
Control Memory : for storing microprogram (Microinstruction)
Data Path
ALU + RegFile PC
Control Unit
Main
Memory
LDA ..
SUB .. IR
Sequencer
(Next Address Gen)
Microinstructions
…………………………
………………………..

17. Machine Instruction vs Microinstruction Format

18. A Micro-Programmed Control Unit Organization
The microinstruction is stored in the Control Memory (ROM).
Control Address Register (CAR) specifies the address of the microinstruction.
The Control Data Register (CDR) may hold the instruction currently being executed.
The next address generator produces the next address (Sequencer).

19. A Micro-Programmed Control Unit Organization
One of the functions of the control word is to determine the address of the next microinstruction to be executed.
This microinstruction may be the next one in sequence
Or may be located somewhere else in the control memory
Therefore, one or more bits that specify how to determine the address of the next microinstruction must be present in the current microinstruction.
The next address may also be a function of status and external control inputs.

20. Next-address generator (sequencer)
Control address register
Control memory (ROM)
Control data register
Control word
Next-address information
External input
Sequencer
»Determine the address sequence that is read from control memory
»Next address of the next microinstruction can be specified several way depending on the sequencer input.
Sequencing Capabilities Required in a Control Storage
Incrementing of the control address register (adder/Incrementer)
A mapping process from the bits of the machine instruction to an address for control memory

21. Mapping of Instructions (Mapping Logic)

22. Control Address Register
A Simple Sequencer Implementation
“000…000”
MUX
Control Address Register
Incrementer +1
Instruction Register
Mapping Logic
010
001
011
100
011
Control Memory
101 En
011
011
011 …
Control Signals (micro-operations)

23. Multiplier Example

24. Multiplier Example Partial products are: 101 x 0, 101 x 1, and 101 x 1
Example: (101 x 011) Base 2
Note that the partial product summation for n digits, base 2 numbers requires adding up to n digits (with carries) in a column.
Note also n x m digit multiply generates up to an m + n digit result (same as decimal).
Partial products are: x 0, 101 x 1, and 101 x 1

25. Example (1 0 1) x (0 1 1) Again
Reorganizing example to follow hardware algorithm:
Multiplier: Register Q
Multiplicand: Register B
Scratchpad: Register A 1 x +
Clear C || A
Multipler0 = 1 => Add B
Addition
Shift Right (Zero-fill C)
Multipler1 = 1 => Add B
Shift Right
Multipler2 = 0 => No Add,
Clear C || A

26. Hardware ? (Data Path + Control)
A Parallel Adder
Switches to enter Multiplier/Multiplicand
Shift Register Q (Multiplier)
Register B (Multiplicand)
Counter (to know when to stop)
Zero detection circuit (input to control)
Shift Register A (scratch pad)
Flip Flop to store Carry of Adder
Detect when Q0 is zero or one (input to control)
A Go signal to start (input to control)
Control Output?
Load, Load_B, Clear_C, Initialize_A, Shift

27. Multiplier Example: Block Diagramn 2 1 IN n
Multiplicand
Counter P
Register B
log n n 2
Zero detect
G (Go) C
Parallel adder
out Z n n
Control Q
Multiplier o
unit C
Shift register A
Shift register Q 4 n
Product
Control signals
OUT

28. Multiplier Example: Block Diagram
The multiplicand (top operand) is loaded into register B(X)
The multiplier (bottom operand) is loaded into register Q(X) C
out n 2 1
Counter P
Zero detect
Control
unit
G (Go)
log Q o Z
Parallel adder
Multiplicand
Register B
Shift register A
Shift register Q
Multiplier
Product
OUT IN
Control signals 4

29. Multiplier Example: Block Diagram
Register C||A is initialized to 0 when G becomes 1.
The partial products are formed in register C||A||Q C
out n 2 1
Counter P
Zero detect
Control
unit
G (Go)
log Q o Z
Parallel adder
Multiplicand
Register B
Shift register A
Shift register Q
Multiplier
Product
OUT IN
Control signals 4

30. Multiplier Example: Block Diagram
Each multiplier bit, beginning with the LSB, is processed
if bit is 1, use adder to add B to partial product;
if bit is 0, do nothing C
out n 2 1
Counter P
Zero detect
Control
unit
G (Go)
log Q o Z
Parallel adder
Multiplicand
Register B
Shift register A
Shift register Q
Multiplier
Product
OUT IN
Control signals 4

31. Multiplier Example: Block Diagram
C||A||Q is shifted right using the shift register
Partial product bits fill vacant locations in Q as multiplier is shifted out
If overflow during addition, the outgoing carry is recovered from C during the right shift C
out n 2 1
Counter P
Zero detect
Control
unit
G (Go)
log Q o Z
Parallel adder
Multiplicand
Register B
Shift register A
Shift register Q
Multiplier
Product
OUT IN
Control signals 4

32. Multiplier Example: Block Diagram
Steps (5 and 6) are repeated until Counter P = 0 as detected by Zero detect.
Counter P is initialized in step 4 to n – 1, n = number of bits in multiplier C
out n 2 1
Counter P
Zero detect
Control
unit
G (Go)
log Q o Z
Parallel adder
Multiplicand
Register B
Shift register A
Shift register Q
Multiplier
Product
OUT IN
Control signals 4

33. Multiplier Example: ASM Chart (continued)
Three states are employed using a Mealy output model:
IDLE - state in which:
input G is used as the condition for starting the multiplication, and
C, A, and P are initialized
MUL0 - state in which conditional addition is performed based on the value of Q0.
MUL1 - state in which:
right shift is performed to capture the partial product and position the next bit of the multiplier in Q0
the terminal count of 0 for down counter P is used to sense completion or continuation of the multiply.

34. Multiplier Example: ASM Chart
IDLE
MUL0 1 G 1 Q
C ←
0, A ←
P ←
n – 1
A ←
A + B,
C ← C
out
MUL1
C ← 0, C || A || Q ← sr C || A || Q,
P ←
P – 1 1 Z

35. Multiplier Example: Control Unit
In implementing a complex control unit, designers usually have to deal (separate) two distinct aspects
The generation of the control signals
Sequencing of the operations (what will happen next)
We can separate the two aspects by dividing the original ASM specification into two parts:
A table that defines the control signals in terms of states and inputs
A simplified ASM chart that represents only transitions from state to state

36. Multiplier Example: Control Signal Table
Bloc
k Dia g
ram
Mod u l e
Register A :
Register B : F
lip-F
lop C
Register Q
Cou n
ter P :

37. Multiplier Example: Control Signal Table
Bloc
k Dia g
ram
Mod u l e Mi cr oo pe ra ti on
Register A : A ←
A ← A + B C || A || Q ← sr C || A || Q
Register B :
B ← IN F
lip-F
lop C
: C ←
C ← C ou t
Register Q
: Q ← IN C || A || Q ← sr C || A || Q
Cou n
ter P :
P ← n – 1 P ← P – 1

38. Multiplier Example: Control Signal Table
Bloc
k Dia g
ram
Contr o l
Mod u l e Mi cr oo pe ra ti on Si gn
al N a me
Register A : A ← I
nitia
liz e
A ← A + B
Load C || A || Q ← sr C || A || Q
Shift_dec
Register B :
B ← IN
Load_B F
lip-F
lop C
: C ← C
lea r _C
C ← C
Load ou t
Register Q
: Q ← IN
Load_Q C || A || Q ← sr C || A || Q
Shift_dec
Cou n
ter P :
P ← n – 1 I
nitia
liz e P ← P – 1
Shift_dec

39. Multiplier Example: ASM Chart
IDLE
MUL0 1 G 1 Q
C ←
0, A ←
P ←
n – 1
A ←
A + B,
C ← C
out
MUL1
C ← 0, C || A || Q ← sr C || A || Q,
P ←
P – 1 1 Z

40. Multiplier Example: Control Signal Table
Bloc
k Dia g
ram
Contr o l
Contr o l
Mod u l e Mi cr oo pe ra ti on Si gn
al N a me
Exp r e
ssi on
Register A : A ← I
nitia
liz e
IDLE · G
A ← A + B
Load MUL0 · Q0 C || A || Q ← sr C || A || Q
Shift_dec M
UL1
Register B :
B ← IN
Load_B LO
ADB F
lip-F
lop C
: C ← C
lea r _C
IDLE ·
G +
MUL1
C ← C
Load — ou t
Register Q
: Q ← IN
Load_Q LO
ADQ C || A || Q ← sr C || A || Q
Shift_dec —
Cou n
ter P :
P ← n – 1 I
nitia
liz e — P ← P – 1
Shift_dec —

41. Multiplier Example: Control Table (continued)
Signals are defined on a register basis
LOADQ and LOADB are external signals controlled from the system using the multiplier and will not be considered a part of this design
Note that many of the control signals are “reused” for different registers.
These control signals are the “outputs” of the control unit
With the outputs represented by the table, they can be removed from the ASM giving an ASM that represents only the sequencing (next state) behavior

42. Example - Sequencing Part of ASM
IDLE 00 1 G
MUL0 01
MUL1 10 1 Z

43. Example: Cont .. Sequencer and Decoder Design
First, define:
States: IDLE, MUL0, MUL1
Input Signals: G, Z, Q0 (Q0 affects outputs, not next state)
Output Signals: Initialize, LOAD, Shift_Dec, Clear_C
State Transition Diagram
Output Function.
Second, find
State Assignments (two bits required)
We will use two state bits to encode the three state IDLE, MUL0, and MUL1.

44. Example: Cont .. Sequencer and Decoder Design
Assuming that state variables M1 and M0 are decoded into states, the next state part of the state table is:

45. Sequence Reg & Decoder
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46. Example: Cont .. Sequencer and Decoder Design
Finding the equations for M1 and M0 is easier due to the decoded states: M1 = MUL M0 = IDLE · G + MUL1 · Z’
Note that since there are five variables, a K-map is harder to use, so we have directly written reduced equations.
The output equations using the decoded states: Initialize = IDLE · G Load = MUL0 · Q Clear_C = IDLE · G + MUL Shift_dec = MUL1

47. Sequencer and Decoder Design
START
Initialize G M D
Clear_C Z C
DECODER
IDLE A0
MUL0 1
MUL1 2
Shift_dec A1 3 M 1 D C
Load Q

48. One FF per State: Trans Rules
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49. One FF Per State Control Unit
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50. Multiplier Example: Flip-flop per State Design Logic Diagram
IDLE
MUL0
MUL1
Initialize
Clear _C
Load
Shift_dec
Clock Z Q 4 1 G 2 5
DEMUX A EN
START
IDLE 00 1 G 01
MUL0
MUL1 10 1 Z

51. Multiplier Microprogrammed
Control

52. Multiplier: Original ASM Chart
IDLE
MUL0 1 G 1 Q
C ←
0, A ←
P ←
n – 1
A ←
A + B,
C ← C
out
The structure of the ASM chart has to change to a Moore-type since no conditional output boxes are permitted.
This means more states will be required
MUL1
C ← 0, C || A || Q ← sr C || A || Q,
P ←
P – 1 1 Z

53. Multiplier: Modified ACM Chart
The modified ACM chart has two extra states
INIT
Add
Besides being a Moore-type circuit, this ASM has only single decision boxes determining the sequencing between states (simplification).
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54. A Micro-Programmed Control Unit Organization
The Control Memory is assumed to be a ROM.
The Control Address Register (CAR) specifies the address of the microinstruction.
The Control Data Register (CFR), which is optional, may hold the microinstruction currently being executed by the data path and the control unit.

55. A Micro-Programmed Control Unit Organization
One of the functions of the control word is to determine the address of the next microinstruction to be executed.
This microinstruction may be the next one in sequence
Or may be located somewhere else in the control memory
Therefore, one or more bits that specify how to determine the address of the next microinstruction must be present in the current microinstruction.
The next address may also be a function of status and external control inputs.

56. A Micro-Programmed Control Unit Organization
The next address generator, in combination with the CAR, is sometimes called a microprogram sequencer.
It determines the sequence of instructions that is read from the control memory.
The address of the next microinstruction can be specified in several ways:
Increment the CAR by one
Loading the CAR
Possible sources for the load operation include:
An address from control memory
An externally provided address
An initial address to start control unit operation +
Load

57. Multiplier: Control Unit
We need to determine three things:
The bits in the control word for the microinstructions
The size of the ROM and the CAR
The structure of the next address generator
We can then proceed to design the microsequencer and write the microprogram for binary multiplication.
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58. Multiplier: (1) Control Signals
Control Signals for the Microprogrammed Multiplier Control Unit:
Initialize
Load
Clear_C
Shift_dec
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59. Multiplier: (1) Control Signals
Control Signals for Microprogrammed Multiplier Control
Initialize
Load
Clear_C
Shift_dec
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60. Multiplier: (1) Control Signals
Microinstruction Control Word Format
Data Path
datapath 3 2 1
Sequencing SD CC LD IT
The remainder of the microinstruction control word is devoted to the sequencing of the control unit.
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61. Multiplier: Sequencing
The approach used to define the addresses is a major decision in the sequencer design.
There are many possible approaches, but two are most typical.
Method #1: Uses two addresses in the microinstruction.
Method #2: Uses only a single address.
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62. Multiplier: Sequencing
Method #1 (two addresses):
Includes the two addresses in the microinstruction controlling the decision.
Based on the value of the decision variable, one of the two address values is loaded into the CAR.
This method permits the arbitrary assignment of addresses to states and ensures that no states need to be added to provide the desired sequencing.
But it requires two addresses in each microinstruction, potentially resulting in a long microinstruction word and wide ROM.
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63. Multiplier: Sequencing
Method #2 (one address):
Uses a counter with parallel load as the CAR
One of the two addresses is obtained from the microinstruction
The other is obtained by simply counting up the CAR
It requires at most one address per microinstruction word.
Assignment of the addresses to the states can be problematic
States may have to be added to provide the desired sequencing
These states can slow the operation of the system due to the added clock cycles needed to pass through them.
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64. Multiplier: (2) Select Field
Microinstruction Control Word Format (Two Addresses)
Selection
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65. Multiplier: SEL Field
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66. Multiplier: Control Word
Microinstruction Control Word Format
Data Path bits
Selection bits
Next Address #0
Next Address #1
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67. Microprogrammed Control Unit for Multiplier
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68. Microprogrammed Control Unit for Multiplier
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69. Microprogrammed Control Unit for Multiplier
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70. Microprogrammed Control Unit for Multiplier
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71. Microprogrammed Control Unit for Multiplier00
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72. Multiplier
The table below gives the register transfer description of the Binary Multiplier Microprogram.
Notice that there are 5 states (thus 5 addresses) each activating a specific part of the system.
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73. Multiplier
The table below gives the microprogram for the binary multiplier in register transfer notation.
There is a microinstruction in the microprogram that corresponds to each of the states in the ASM chart
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74. Microprogrammed Control
Given this brief introduction to hardwired and mircro-porgrammed control unit design, we are now prepared to consider more complex control units for programmable digital systems.
Our specific focus will start with simple computers, thereby building a basis for studying CPU designs.
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75. End Slides

76. VHDL Code P2 P1 P3 Similar to Sequencer Process that will
depend on clock
event to reset system
to Idle State and
implement state_register
based on CLK
Process that will act as a
sequencer that will dictate
the state you are in given
the input
Process that will control
your data path
(If you have a data path!) P3
Similar to Sequencer

77. Implement Using VHDL Y Z X S IDLE 00 G 1 LOAD 01 10 ADD1
LOAD 01 10 S
ADD
What are the Inputs?
Remember that this
is a state machine
and we have to
start somewhere at
power up!

78. VHDL Code -- VHDL Code entity declaration library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sequential_machine is
port (CLK, RESET, G, S : in std_logic;
X,Y, Z : out std_logic);
end sequential_machine;

79. VHDL Code: Architecture
architecture behavior of sequential_machine is
type state_type is (IDLE, LOAD, ADD);
signal state, next_state : state_type;
begin
end behavior;
State_register: process (CLK)
.....
Next_state_func: process (G,S,state)
......
Datapath_func: process (CLK)

80. VHDL Code: State-Register Process
State_Register: process (CLK, RESET)
begin
if (RESET = ‘1’) then
state <= IDLE;
elsif (CLK'event and (CLK = '1')) then
state <= next_state;
end if;
end process;

81. VHDL Code: Next-State Process
-- VHDL Code for next_state_func
next_state_func: process (G,S,state)
begin
case state is
when IDLE =>
if G = ‘1’ then
next_state <= LOAD;
else
next_state <= IDLE;
end if;
when LOAD =>
next_state <= ADD;
when ADD =>
if S = ‘1’ then
end case
end process; X Y Z
IDLE 00 G 1
LOAD 01 10 S
ADD

82. VHDL Code: datapath Process
-- VHDL Code for datapath_func
Output_func: process (state)
begin
case state is
when IDLE =>
X <= 1;
when LOAD =>
Y <= 1;
when ADD =>
Z < =1
end case
end process; X Y Z
IDLE 00 G 1
LOAD 01 10 S
ADD

83. VHDL for Binary Multiplier - 1
-- Binary Multiplier with n = 4
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity binary_multiplier is
port(CLK, RESET, G, LOADB, LOADQ: in std_logic;
MULT_IN: in std_logic_vector(3 downto 0);
MULT_OUT: out std_logic_vector(7 downto 0));
end binary_multiplier;

84. VHDL for Binary Multiplier - 1
-- Binary Multiplier with n = 4
architecture sequential of binary_multiplier is
type state_type is (IDLE, MUL0, MUL1);
signal state, next_state: state_type;
signal P: std_logic_vector(1 downto 0);
signal A,B,Q: std_logic_vector(3 downto 0);
signal C,Z: std_logic;
begin
Z <= P(1) NOR P(0);
MULT_OUT <= A &Q
state_register: process (CLK, RESET)
……..
next_state_func: process (G, Z, state)
datapath_func: process (CLK)
end sequential;

85. VHDL for Binary Multiplier - 2
-- state register
state_register: process (CLK, RESET)
begin
if (RESET = '1') then
state <= IDLE;
elsif (CLK'event and (CLK = '1')) then
state <= next_state;
end if;
end process;

86. VHDL for Binary Multiplier - 3
-- next state function
next_state_function: process (state, G, Z)
begin
case state is
when IDLE =>
if (G = '1') then
next_state <= MUL0;
else
next_state <= IDLE;
end if;
when MUL0 =>
next_state <= MUL1;
when MUL1 =>
if (Z = '1') then
end case;
end process;

87. VHDL for Binary Multiplier - 4
-- datapath function
Datapath_func: process (CLK)
variable CA: std_logic_vector (4 downto 0);
begin
if (CLK'event and (CLK = '1')) then
if (LOADB = '1') then
B <= MULT_IN;
elsif (LOADQ = '1') then
Q <= MULT_IN;
end if;
case state is
when IDLE =>
if G = '1‘ then
C <= ‘0’;
A <= "0000";
P <= “11”;

88. VHDL for Binary Multiplier - 4
-- cont ….datapath function
case state is
…….
when MUL0 =>
if Q(0) = ‘1’ then
CA := (‘0’ & A) + (‘0’ & B);
else
CA <= C & A;
end if;
C <= CA(4);
A < CA (3 downto 0);
when MUL1 =>
C =< ‘0’
A <= C & A(3 downto 1);
Q <= A(0) & Q(3 downto 1);
P = P – “01”;
end case;
end process