1. Lecture 6: Functions of Combinational Logic
Half-Adder
Basic rules of binary addition are performed by a half adder, which has two binary inputs (A and B) and two binary outputs (Carry out and Sum).
The inputs and outputs can be summarized on a truth table.
The logic symbol and equivalent circuit are: B A S + = A B S
Cout A B S
Cout
C = AB

2. Lecture 6: Functions of Combinational Logic
Full-Adder
By contrast, a full adder has three binary inputs (A, B, and Carry in) and two binary outputs (Carry out and Sum). The truth table summarizes the operation. S A S
Sum B
Cout
Cout
Cin
Cin
A full-adder can be constructed from two half adders as shown:
Symbol S A B S
Cout A A S
Sum B B
Cout
Cin
Cout

3. Lecture 6: Functions of Combinational Logic
Full-Adder A B S
Cout 1
Sum 1
Example 1
For the given inputs, determine the intermediate and final outputs of the full adder. 1
Cout 1
The first half-adder has inputs of 1 and 0; therefore the Sum =1 and the Carry out = 0.
Solution
The second half-adder has inputs of 1 and 1; therefore the Sum = 0 and the Carry out = 1.
The OR gate has inputs of 1 and 0, therefore the final carry out = 1.

4. Lecture 6: Functions of Combinational Logic
Full-Adder
Notice that the result from the previous example can be read directly on the truth table for a full adder. A B S
Cout 1
Sum

5. Lecture 6: Functions of Combinational Logic
Parallel Adders
A4 A3 A2 A1 + B4 B3 B2 B1 =?
Full adders are combined into parallel adders that can add binary numbers with multiple bits. A 4-bit adder is shown. A B S
Cout
Cin
A1 B1 S1 C0 S2 S3 S4 C1 C2 C3 C4
A2 B2
A3 B3
A4 B4
The output carry (C4) is not ready until it propagates through all of the full adders. This is called ripple carry, delaying the addition process.

6. Lecture 6: Functions of Combinational Logic
Parallel Adders
The logic symbol for a 4-bit parallel adder is shown. This 4-bit adder includes a carry in (labeled (C0) and a Carry out (labeled C4).
Binary number A
Binary number B
Input carry
4-bit sum
Output carry 1 2 3 4 C0 C4 S
The 74LS283 is an example. It features look-ahead carry, which adds logic to minimize the output carry delay. For the 74LS283, the maximum delay to the output carry is 17 ns.

7.   例. 用74283构成将8421BCD码转换为余3码的 码制转换电路 。 8421码 余3码 0000 0011 0001
8421码输入 1 1
0000
+0011
0011
0001
+0011
0100 CO
0010
+0011
0101  
余3码输出

8. 4、减法运算 若n位二进制的原码为N原，则与它相对应的2 的补码为 N补=2N N原 补码与反码的关系式 N补=N反+1
设两个数A、B相减，利用以上两式 可得
A B=A+B补2n=A+B反+12n
在实际应用中，通常是将减法运算变为加法运算来处理，即采用加补码的方法完成减法运算。

9. 舍弃 舍弃 1）AB  0的情况。 2）AB <0的情况。 A= 0010 ，B=0101 A=0101 ，B=0010 舍弃 舍弃
当A–B  0时，舍弃的进位为1，所得 结果就是差的原码，不需再求反补。
当A–B < 0时，舍弃的进位为0，所得结果是补码，要得到原码需再求补。

10. 输出为原码的4位减法运算逻辑图

11. Lecture 6: Functions of Combinational Logic
Comparators
The function of a comparator is to compare the magnitudes of two binary numbers to determine the relationship between them. In the simplest form, a comparator can test for equality using XNOR gates.
Example
How could you test two 4-bit numbers for equality?
AND the outputs of four XNOR gates.
Solution A1 B1 A2 B2
Output A3 B3 A4 B4

12. Lecture 6: Functions of Combinational Logic

13. Lecture 6: Functions of Combinational Logic
Comparators
IC comparators provide outputs to indicate which of the numbers is larger or if they are equal. The bits are numbered starting at 0, rather than 1 as in the case of adders. Cascading inputs are provided to expand the comparator to larger numbers. A1 A0 A2 A3 B1 B0 B2 B3
Cascading inputs
COMP
A = B
A < B
A > B 3 A
Outputs
The IC shown is the 4-bit 74LS85.

14. Lecture 6: Functions of Combinational Logic
Comparators
IC comparators can be expanded using the cascading inputs as shown. The lowest order comparator has a HIGH on the A = B input.
Outputs A1 A0 A2 A3 B1 B0 B2 B3
COMP
A = B
A < B
A > B 3 A A5 A4 A6 A7 B5 B4 B6 B7
+5.0 V
LSBs
MSBs

15. Lecture 6: Functions of Combinational Logic
B15A15~B12A12
B11A11~B8A8
B7A7~B4A4
B3A3~B0A0
IC comparators can be expanded using Parallel inputs as shown.

16. Lecture 6: Functions of Combinational Logic
1、编码器 (Encoder)
具有编码功能的逻辑电路。
编码：赋予二进制代码特定含义的过程称为编码。
编码器的逻辑功能：
能将每一个编码输入信号变换为不同的二进制的代码输出。
如BCD编码器：将10个编码输入信号分别编成10个4位码输出。
如：8421BCD码中，用1000表示数字8
如：ASCII码中，用 表示字母A等

17. Lecture 6: Functions of Combinational Logic
Encoders
An encoder accepts an active logic level on one of its inputs and converts it to a coded output, such as BCD or binary. 1
The decimal to BCD is an encoder with an input for each of the ten decimal digits and four outputs that represent the BCD code for the active digit. The basic logic diagram is shown. There is no zero input because the outputs are all LOW when the input is zero. A0 2 3 A1 4 5 A2 6 7 8 A3 9

18. Lecture 6: Functions of Combinational Logic
Encoders
Show how the decimal-to-BCD encoder converts the decimal number 3 into a BCD 0011.
Example
The top two OR gates have ones as indicated with the red lines. Thus the output is 0111.
Solution 1 1 1 A0 2 3 1 A1 4 5 A2 6 7 8 A3 9

19. Lecture 6: Functions of Combinational Logic
Encoders
The 74HC147 is an example of an IC encoder. It is has ten active-LOW inputs and converts the active input to an active-LOW BCD output.
VCC
This device is offers additional flexibility in that it is a priority encoder. This means that if more than one input is active, the one with the highest order decimal digit will be active.
HPRI/BCD
Decimal input
BCD output
74HC147
The next slide shows an application …
GND

20. Lecture 6: Functions of Combinational Logic
VCC
Encoders
Keyboard encoder
HPRI/BCD
BCD complement of key press
74HC147
The zero line is not needed by the encoder, but may be used by other circuits to detect a key press.

21. Lecture 6: Functions of Combinational Logic
Code converters
There are various code converters that change one code to another. Two examples are the four bit binary-to-Gray converter and the Gray-to-binary converter.
Show the conversion of binary 0111 to Gray and back.
Binary-to-Gray Gray-to-Binary
MSB
LSB 1 1 1 1 1 1 1 1

23. Lecture 6: Functions of Combinational Logic
Decoder: a digital circuit that detects the presence of a specified combination of bits on its inputs and indicates the presence of that code by a specified output level.
In general, a decoder has n input lines to handle n bits and from one to 2n outlines to indicate the presence of one or more n-bit combinations.
The Basic Binary Decoder
The 4-bit Decoder --> 74HC154 IC Decoder
The BCD-to-Decimal Decoder --> 74HC42 IC Decoder
The BCD-to-7-Segment Decoder --> 74LS47 IC Decoder
Analyze and describe the function of each decoder.
Apply decoders to specific applications.

24. 6-5 Decoders 1 The Basic Binary Decoder Determine the logic
required to decode the binary number 1011
by producing a HIGH level on the output.
Example 6-8, P175
In the representation of a binary number, the LSB is the right-most bit in a horizontal arrangement and the topmost bit in a vertical arrangement.

25. 6-5 Decoders 1 The Basic Binary Decoder
Develop the logic required to detect the binary code 1011 by and produce an active-LOW output.
You wish to detect only by the presence of the codes 1100, 0001, and An active-HIGH output is required to indicate their presence. Develop the minimum decoding logic with a simple output that will indicate when any one of these codes is on the inputs. For any other code, the output must be LOW.

26. 74HC138 1 × X A2 E3
输 出
输 入 A1 A0

27. 74HC138
逻辑符号

28. 用一片74HC138实现函数
首先将函数式变换为最小项之和的形式
在译码器的输出端加一个与非门，即可实现给定的组合
逻辑函数.

29. 用译码器74HC138实现数据分配器
当ABC = 010 时，Y2=D 1 C B A

30. 6-5 Decoders
2 The 4-bit Decoder

31. 6-5 Decoders
2 The 4-bit Decoder (74HC154)

32. 6-5 Decoders 2 The 4-bit Decoder (74HC154) 4 input lines.
2 ship select inputs.
Enable function: required the two select inputs be LOW.
The enable gate output is connected to an input of each NAND gate.
If the enable gate is not activated by a OW on both inputs, the 16 outputs will be HIGH.

33. 6-5 Decoders
Example 6-10, P216
A certain application requires that a 5-bit number be decoded. Use 74HC154 decoders to implement the logic. The binary number is represented by the format A4A3A2A1A0.

34. 6-5 Decoders 3 The BCD-to-Decimal Decoder (74HC42)
BCD: Binary Coded Decimal.
BCD: each decimal digit, 0 through 9, is represented by a binary code of 4 bits.
There are only 10 code groups in the BCD system.
BCD-to-Decimal Decoder : converts each BCD code into one of ten possible decimal digit indications.
Referred as 4-line-to-10-line decoder
1-of-10 decoder

35. 6-5 Decoders 3 The BCD-to-Decimal Decoder (74HC42)
Recall from 4-2 Determining Standard Expression from a Truth Table
In the output column, find the output that equals 1.
For each input combination whose output is 1, convert the corresponding input binary values to product term by replacing each 1 with the corresponding variable and each 0 with the corresponding variable complement.

36. 6-5 Decoders
3 The BCD-to-Decimal Decoder (74HC42)

37. 6-5 Decoders
3 The BCD-to-Decimal Decoder (74HC42)

38. 6-5 Decoders 4 The BCD-to-7-Segment Decoder
7-segment displays are driven by logic circuits that decode a BCD number and activate the appreciate digits on the display.
Selected segments are activated to create each of the ten decimal digits as well as certain letters of the alphabet.
The BCD-to-7-Segment decoder accepts the BCD code on its input and provides output to drive 7-segment display devices.

39. 6-5 Decoders 4 The BCD-to-7-Segment Decoder (74LS47) Lamp test
Ripple blanking input
Blanking input/ ripple blanking output
all of the seven segments in the display are turned on.
Lamp test is used to verify that no segments are burned out.

40. 6-5 Decoders 4 The BCD-to-7-Segment Decoder (74LS47)
Zero suppression: used for multidigit displays to blank out unnecessary zeros.
Leading zero suppression: Blanking the zeros at the front of a number.
Leading zero suppression: Blanking the zeros at the back of a number.
0000 is on BCD inputs and , all of the segment outs are nonactive.
Result in the display to be blank and .

41. 6-5 Decoders 4 The BCD-to-7-Segment Decoder (74LS47)
The highest-order digit position is always blanked if a zero code is on its BCD inputs.
The of each decoder is connected to the of the nest lowest-order decoder so that all zeros to the left of the first non-zero digit are blanked.

42. 6-5 Decoders 4 The BCD-to-7-Segment Decoder (74LS47)
Problem 22, P348
A 7-segment decoder drives the display. If the waveforms are applied as indicated, determine the sequence of digits that appears on the display.

43. 6-6 Multiplexers (Data Selectors)
In computer networks, a shard bus is one that is connected to all the microprocessors in the system in order to exchange data.
A shard bus contains input/put devices that can be accessed by all the microprocessors in the system,
Access to the shard bus is controlled by a multiplexer that allows only one microprocessor at a time to use the system’s shard bus.
Multiplexer: allows digital information from several sources to be routed to a single line for transmission over that line to a common destination.
The basic multiplexer has several data-input lines and a single output line.
It has data-select inputs, which permit digital data on any one of the inputs to be switched to the out line.
Multiplexers are known as data selector.
Explain the basic operation of a multiplexer.
Describe the 74LS151 multiplexer.
Use 74LS151 to handle more data inputs and implement a logic function.

44. 6-6 Multiplexers (Data Selectors)
1 4-input Multiplexer
In a multiplexer, data goes from several lines to one line.
With the two data-select bits, any one of the 4 data-input lines can be selected.
A 2-bit code on the data-select inputs will allow the data on the selected data input to pass through to the data output.

45. 6-6 Multiplexers (Data Selectors)
1 Implementation of 4-input Multiplexer

46. 6-6 Multiplexers (Data Selectors)
3 Operation of 4-input Multiplexer with Waveforms

47. 6-6 Multiplexers (Data Selectors)
4 The 74LS151 8-input Multiplexer
3 data-select bits are required to select any one of the 8 data inputs.
When , it allows the selected input data to pass through to the output.

48. 6-6 Multiplexers (Data Selectors)
5 Expand 74LS151 to Handle 16 Data Inputs
4 data-select bits are required to select any one of the 16 data inputs.
input is used as the most significant data-select bit.
When the left 74LS151 is enabled.
One of the data inputs (D0-D7) is selected by the three data-select bits S2, S1, and S0.
When the right 74LS151 is enabled.
One of the data inputs (D8-D15)
is selected by the three
data-select bits S2, S1,
B and S0.

49. 6-6 Multiplexers (Data Selectors)
5 74LS151-A Function Generator
74LS151 can be used as a logic function generator.

50. 6-6 Multiplexers (Data Selectors)
5 74LS151-A Function Generator
Example 16, P325
Implement the logic function specified in the table with logic gates and by using a 74LS151, respectively.

51. 实现并行数据到串行数据的转换

52. 6-6 Multiplexers (Data Selectors)
Used as a data selector.
The basic multiplexer has several data-input lines and a single output line.
It has data-select inputs, which permit digital data on any one of the input to be switched to the out line.
Used as a logic function generator. .
The data input selected is connected to a HIGH.
The others must be connected to a LOW.
ASSIGNMENT
Reading- Chapter 6 P
Analyzing-Examples 6-14, 6-15， and 6-16.
Homework-Problems 28, and 30 (P349).