1. Update on & SVT readout chip requirements
Jan. 2011
Giuliana Rizzo
Universita’ & INFN Pisa
G. Rizzo
SuperB –SVT readout chip specs – 20/1/2011

2. SuperB –SVT readout chip specs – 20/1/2011
Project Status (I)
The SuperB project has been approved by the Italian Government (Dec ) with an initial funding for 2010 as a part of a multiannual funding program.
19 M€ assigned for 2010 to INFN for infrastructure and accelerator.
Detector will be funded with the INFN standard budget and by other International funding Agencies
Agreement with US to contribute with parts of the accelerator and detector of the SLAC B-Factory.
Schedule:
Complete TDR in 2011
Start data taking in 5 years
Site (Italy!)
Selection before the summer
International Committee already appointed.
Several options still open:
Roman area (INFN Frascati Lab., Tor Vergata Campus)
Area close to Brindisi
Other site under evaluation
G. Rizzo
SuperB –SVT readout chip specs – 20/1/2011

3. SuperB –SVT readout chip specs – 20/1/2011
Project Status (II)
Growing international interest and participation with international collaboration being formed.
MOUs for TDR signed with France, Russia and SLAC and a letter of support from Canada.
Situation with US groups “in evolution”
Istitutions already involved in SVT:
Several INFN groups in Italy (Bo,Mi,Pi,PV/BG,Ts,To,RMIII)
Interest from UK (RAL, Queen Mary)
After project approval hope to enlarge the collaboration with new groups that express their interest.
Next Superb Meeting:
4-9 April next Workshop (Detector – Physics) in Frascati
End of May in Elba: 1st SuperB Collaboration Meeting.
G. Rizzo
SuperB –SVT readout chip specs – 20/1/2011

4. The SuperB Silicon Vertex Tracker
BaBar SVT
5 Layers of double-sided Si strip sensor
Low-mass design. (Pt < 2.7 GeV)
Stand-alone tracking for slow particles.
97% reconstruction efficiency
Resolution ~15μm at normal incidence
40 cm
30 cm
20 cm
Layer0
old beam pipe
new beam pipe
SVT
SuperB SVT based on Babar SVT design for R>3cm. BUT:
Reduced beam energy asymmetry (7x4 GeV vs. 9x3.1 GeV) requires improved vertex resolution (~ factor 2 needed)
Layer0 very close to the IP (R~ 1.5 cm) with low material budget
Layer0 area 100 cm2
Background levels depends steeply on radius
 Layer0 needs to have fine granularity and radiation tolerance
Bp p decay mode, bg=0.28, beam pipe X/X0=0.42%, hit resolution =10 mm
Dt resolution (ps)
Layer0 subject to large background and needs to be extremely thin:
Track rate > 5MHz/cm2, > 3MRad/yr, < 1 %X0
G. Rizzo
SuperB –SVT readout chip specs – 20/1/2011

5. SuperB SVT Layer 0 technology options
Striplets option: mature technology, not so robust against background occupancy.
Marginal with back. track rate higher than ~ 5 MHz/cm2
Moderate R&D needed on module interconnection/mechanics/FE chip (FSSR2 or new chip)
Hybrid Pixel option: viable, although marginal.
Reduction of total material needed!
Reduction in the front-end pitch to 50x50 μm2 with data push readout (developed for DNW MAPS)
 FE prototype chip (4k pixel, ST 130 nm) now under test.
CMOS MAPS option: new & challenging technology.
Sensor & readout in 50 μm thick chip!
Extensive R&D (SLIM5-Collaboration) on
Deep N-well devices 50x50μm2 with in-pixel sparsification.
Fast readout architecture implemented
CMOS MAPS (4k pixels) successfully tested with beams.
Thin pixels with Vertical Integration: reduction of material and improved performance.
Two options are being pursued (VIPIX-Collaboration)
DNW MAPS with 2 tiers
Hybrid Pixel: FE chip with 2 tiers + high resistivity sensor
Complexity
Sensor
Digital tier
Analog tier
Wafer bonding & electrical interconn.
G. Rizzo
SuperB –SVT readout chip specs – 20/1/2011

6. SuperB –SVT readout chip specs – 20/1/2011
Layer0 Strategy
Plan
Start data taking (~ 2016) with striplets (baseline option for TDR):
Better physics performance (lower material ~0.5% vs 1% hybrid pixel, MAPS or thin hybrid pixel in between but not yet mature!)
Upgrade Layer0 to pixel (Hybrid or CMOS MAPS), more robust against background, for the full Luminosity (1-2 yrs after t0).
SVT Mechanics will be designed to allow a quick access/removal of Layer0
~10% better
~20% more Luminosity
G. Rizzo
SuperB –SVT readout chip specs – 20/1/2011

7. Layer0 striplets design
r= 15 mm
Layer0 striplets design
- Geometrical acceptance: 300 mrad in FW and BW sides
- Layer0 radius R~15mm, with 8 double sided modules:
double sided Si detector, 200 mm thick with striplets (45o w.r.t det. edges) readout pitch 50 mm. Sensor 13x97 mm2
multi-layer fanout circuits are glued on each sensor, connecting Si strips to Front End Electronics. 2fanouts/side are needed
fanout extends twice wider than the detector, to allow 50 mm pitch on traces).
HDI are double sided with 7 readout chip/side
HDI
Readout Right
Readout Left z
Si detector
1st fanout, 2nd fanout
G. Rizzo
SuperB –SVT readout chip specs – 20/1/2011

8. SuperB –SVT readout chip specs – 20/1/2011
To allow the entire Layer0 module to fit inside the Layer1 radius (~30mm) the module is bent around the fanout extension
G. Rizzo
SuperB –SVT readout chip specs – 20/1/2011

9. Update on readout chip specs (I)
Background hit rate expected (Full Lumi=1036, Radius~1.5 cm, sensor thickness 200 mm)  225 MHz/cm2 (safety x5 included)
Striplets area ~ 0.01 cm2
10% occupancy in 50 ns time window hard limit for tracking.
Some key requirements for striplets readout chip:
Peaking time <=25 ns (Effi with 100 ns dead time is ~ 83 %)
Hit rate/channel 2 MHz
BCO clock 60 MHz (high timestamp granularity)
Triggered architecture with pipeline depth ~10 us (trigger latency)
Background in Layer1-2 one order of magnitude smaller, larger strip area  hit rate/channel ~ 500kHz.
Longer shaping time can be used O( ns)
G. Rizzo
SuperB –SVT readout chip specs – 20/1/2011

10. Update on readout chip specs (II)
Outer layers (13-15 cm)
Long modules (Layers4-5) need for a signal peaking time in the range 500 ns – 1 ms to reduce the thermal noise contribution from the strip distributed resistance (see Valerio’s slides Sept. 2010)
same triggered architecture could be used in ext. layers (hit rate much smaller O(10 kHz)?
Requirements for striplets (+L1/2) & external layers quite different
need to develop 2 different chips?
Evolution of existent readout chips can be used?
Which technology (CMOS 0.25 um or switch to 0.13 um) ?
G. Rizzo
SuperB –SVT readout chip specs – 20/1/2011

11. SuperB –SVT readout chip specs – 20/1/2011
backup
G. Rizzo
SuperB –SVT readout chip specs – 20/1/2011

12. Background hit frequency
G. Rizzo
SuperB –SVT readout chip specs – 20/1/2011