1. Presented by Jim Seton Prepared by Jim Seton
Understanding Sampling rate vs Data rate. Decimation (DDC) and Interpolation (DUC) Concepts TIPL 4701
Hello, and welcome to the TI High Speed Data Converter Lab that will help a user understand the difference between a data converter sample rate versus data rate. In this video, we will explain the difference between these two commonly used terms along with a high level explanation of decimation and interpolation, which due to these two digital data processing techniques, either decrease or increase the converter data rate.
Presented by Jim Seton
Prepared by Jim Seton

2. Table of Contents Input Data Rates Why lower data rates are required
Sample rate vs Data rate
What is Decimation
Time/Frequency Domain Views
Digital Down Converters (DDC)
Advantages and Disadvantages
What is Interpolation
Digital Up Converters (DUC)
Sample rate vs Data rate vs SerDes rate (JESD204B)
DAC and ADC examples
This video will cover data converter input and sample data rates, digital down converters or DDC that will perform decimation, digital up converters or DUC, that will perform interpolation, key advantages and disadvantages to using these functions, and a brief section on JESD204B Serdes rates, and how they are related to the data converter sample and data rates.

3. Sample Rate vs Data Rate
Sampling rate (Fs) is the speed at which the data converter (ADC) is sampling an analog input or sending out (DAC) an analog output
Data rate is the rate of the digital output data from an ADC or digital input data rate to a DAC
In many cases, these are NOT the same rate.
For instance, ADS54J60
- 16 bit, dual ADC with sample rate = 1Gsps
Decimate by 2 mode, data output rate = sample rate / 2 = 500Msps
Decimate by 4 mode, data output rate = sample rate / 4 = 250Msps
The sample rate is the speed at which an ADC data converter is sampling an analog input or a DAC data converter is sending out an analog output.
This rate is usually the external clock rate that is supplied to these converters. Some of the new converters though, such as the TI DAC38J84 and other parts in this family, have internal PLL’s, that provide an option to create the high speed sample clock using a slower input clock. This sometimes confuses the user when they enter the sample rate information in the GUI’s used by our customer EVM’s.
The data rate is the rate of the digital output data from an ADC or the digital input data rate to a DAC . In many cases, these are NOT the same rate as the sample clock. For example, if a user was operating an ADS54J60 ADC in decimation by 2 mode at a sample rate of 1Gsps, the actual data rate leaving the device will be 1Gsps divided by 2 or 500Msps. If the user was using decimate by 4 mode, this would be 250Msps. Keep in mind that this is the equivalent parallel data rate and not the serdes rate of the output pins of this device. This will be discussed later in this video.

4. Input Data Rates
Higher sampling rates are required for sampling at RF and for frequency planning around spurious areas
Data rates can not operate at those speeds
Limited by processor or FPGA rate
Limited by available I/O on the device
Implement
Interpolation/Decimation in order to keep data rates reasonable
Rule of thumb:
Select data rate to support bandwidth of the signal
Select sampling rate to support spectral purity
With the new higher sampling data converters, higher data rates are required. In many cases these rates are to high for the data converter device or the FPGA/ASIC that is receiving or driving the data to the data converter. Another reason may be the number of IO’s available. In either case, the data rate usually needs to be reduced, and to this, interpolation and decimation are used. When using decimation or interpolation, a good rule of thumb is to select a data rate that can support the bandwidth of the signal and a sampling rate that can support spectral purity.

5. Decimation Concepts
In this next section, we will discuss decimation concepts. This will include a definition, time versus frequency comparison, advantages and disadvantages, and some example TI parts that are using decimation. 5

6. What is Decimation?
Decimation decreases the sample rate of a signal by removing samples from the data stream
Decimation includes digital low pass (anti-aliasing) filter followed by a decimator
The operation is equivalent to utilizing an analog anti-aliasing filter at fc = FS /2M and sampling a converter at Fd = FS /M, where M = decimation count (i.e. 2)
Decimation is used to:
Decrease the ADC data rate to reasonable levels for data capture
Maintain high output sampling rate for more flexible frequency planning
Take advantage of decimation filtering for improved spectral performance
What exactly is decimation. In digital signal processing, decimation is the process of reducing the sampling rate of a signal.  The term downsampling usually refers to one step of the process, but sometimes the terms are used interchangeably.  Complementary to upsampling, or interpolation, which increases sampling rate, decimation is a specific case of sample rate conversion in a multi-rate digital signal processing system. When decimation is performed on a sequence of samples of a signal or other continuous function, it produces an approximation of the sequence that would have been obtained by sampling the signal at a lower rate. This is accomplished by removing samples from the data stream.
Decimation will usually include a digital low pass or anti-aliasing filter followed by the decimator. This operation is like using an analog anti-aliasing filter at a center frequency equal to the sample rate divided by the decimation factor.
The decimation factor is usually an integer or a rational fraction greater than one. This factor divides the sampling rate or can be equivalent to multiplying this number by the output data rate to determine the actual sampling rate used by the ADC.
Decimation is used to decrease the sample rate to levels that the devices can handle, allows for high sampling rates for more flexible frequency planning, and filtering that provides improved spectral performance.

7. Time/Freq Domain View of Decimation
Images created with each decimation
Low Pass filter provides anti-aliasing protection
Data rate reduced for easier processing
In this slide, an example of the decimation function is shown in both the Time domain and frequency domain. When decimation is performed, images are created as shown in the frequency domain plots. The signal and images around the sample rate of the converter will shift down to the sample rate/2 in this example. The signal and images at 2Fs will shift down to Fs and so on. Low pass filters are then used to provide anti-aliasing protection which will remove these images and allow for a clean spectrum at a much lower data rate.

8. Typical DDC Block Diagram (ADS54J60 Data Sheet)
Data sheets usually include block diagrams showing the functions available of the DDC. This slide is showing an example of the DDC functions available inside the ADS54J60 ADC from TI. As you can see from this diagram, this part offers several functions, including a decimate by 2 mode, decimate by 4 mode, mixer shift option followed by decimate by 4 block and a DDC bypass mode.
As mentioned early, decimation is accompanied by filtering, as can be seen in this block diagram. This part has options for a LPF or HPF in dec by 2 mode. In dec by 4 mode, it offers 4 different center frequency options for the BPF.

9. Advantages and Disadvantages
Key Decimation Advantage
Decimation provides SNR processing gain
Frequency Domain View Signal remains constant
Noise power is reduced by decimation filter
Improved SNR performance
Time Domain View Form over averaging samples to reduce overall noise
Decimation “Penalty”
Increased digital power consumption
More digital logic required
Reduced signal bandwidth capability
Using decimation has advantages as well some disadvantages. The advantages are it will provide SNR processing gain, the frequency domain view of the signal remains constant, the noise power is reduced by the decimation filter, SNR performance improves, and due to averaging samples, the overall noise of the converter is reduced.
Using decimation though does not come without some cost. Some of the disadvantages are more digital logic is required. Using more digital logic will also cost more power. And the overall signal bandwidth capability will be reduced.

10. ADC’s with DDC ADC32RF45/80 Family ADC12J4000/2700/1600 Family
ADC32RF45 Dual-channel, 14-bit, 3GSPS Supports DDC (decimation /4 to /32) modes and bypass DDC mode.
ADC32RF80 Dual-channel, 14-bit, 3 GSPS Supports only DDC modes (decimation /4 to /32)
ADC12J4000/2700/1600 Family
Single-channel 12-bit, 1.6 / 2.7 / 4GSPS, support DDC (decimation /4 to /32)
ADS54J20/40/42/60/69 Family
Dual-channel 16,14,12-bit, 625MHz / 1GSPS, support DDC (decimation /2 and /4)
Some examples of TI parts that have an internal decimation function.

11. INTEROLATION Concepts
In this next section, we will discuss interpolation concepts. This will include a definition, time domain view, frequency domain view, advantages and disadvantages, and some example TI parts that are using interpolation. 11

12. Insert a 0 between each sample (zero stuffing / up sampling)
Interpolation increases the sample rate of a signal without affecting the signal itself
The steps for 2x interpolation are as follows:
Insert a 0 between each sample (zero stuffing / up sampling)
Filter the resulting images from the up sample process
Repeat another 2x interpolation to get 4x, and again for 8x
Cascading multiple 2x stages to increase interpolation is best due to efficient half-band filters.
Interpolation is used to:
Increase the DAC output rate to allow for higher DAC output frequencies
Shift the DAC images further from the desired band of interest
Allow for a wider Nyquist zone for more flexible frequency planning
Maintain reasonable input data rates
What exactly is interpolation. In digital signal processing, interpolation or up-sampling, is the process of increasing the sampling rate of a signal without affecting the signal itself.
Interpolation is a method of constructing new data points within the range of a discrete set of known data points.
The typical method used to perform interpolation is as follows: Insert a logic “0” between each sample. This is known as zero stuffing or up sampling.
Filter the resulting images created from the up sample process. This would create a 2x interpolation. To get 4x interpolation, repeat this process again. For 8x, repeat again and so on.
This cascading method is preferred as it increases the efficiency of the required half-band filters. With interpolation, the DAC output rate can be increased, the images can be shifted further from the desired band of interest, allow for a wider Nyquist zone, and maintain reasonable digital data rates to the DAC.

13. Time Domain View of Interpolation
0’s are inserted between the original samples
- Adding a 0 does not change the spectral content, just sampling frequency
- Widens the unique BW of the signal
Low-pass (band-limiting) filtering fills in the missing levels between the original samples
This slide is showing the function of interpolation in the time domain. This examples shows 3 zero’s being inserted between samples. Adding zeros does not change the spectral content of the signal. It just widens the bandwidth. Then using filtering, such as a low pass filter, the samples that were added are adjusted to fill in the missing levels between the actual samples, as shown in the bottom diagram.

14. Frequency Domain View of Interpolation
This next slide is showing a frequency domain view of interpolation. The top diagram is a typical output of a digital up converter before any filtering is applied.
The second diagram is showing the effects of 2x interpolation filter. This will attenuate the odd F data images but not the even order images. The third diagram is showing the effects of the next stage of filtering that is required. Since the odd order images are now removed, this next filtering stage can also use a LPF, but at a higher frequency, allowing it to attenuate the remaining odd images, as show in the bottom diagram.

15. Typical DUC Filter response (DAC38J84 Data Sheet)
Data sheets should show the filter response of the interpolation filters of the device. Figure 60 and Figure 61 in this slide show the magnitude spectrum response for the FIR0, FIR1, FIR2 and FIR3interpolating filters where fin is the input data rate to the FIR filter. Other figures can show the composite filter response for individual interpolation settings.

16. Advantages and Disadvantages
Key Interpolation Advantage
Shift the DAC images further from the band of interest…easier filtering
Allow for a wider Nyquist zone for more flexible frequency planning
Reduces NSD as quantization noise is spread over a wider Nyquist band
Maintain reasonable input data rates; achieve higher output frequencies
Interpolation “Penalty”
Increased digital power consumption
More digital logic required
Input BW limited by interpolation filters. BW = 0.4 * Fdata
Using decimation has advantages as well some disadvantages. The advantages are it will provide SNR processing gain, the frequency domain view of the signal remains constant, the noise power is reduced by the decimation filter, SNR performance improves, and due to averaging samples, the overall noise of the converter is reduced.
Using decimation though does not come without some cost. Some of the disadvantages are more digital logic is required. Using more digital logic will also cost more power. And the overall signal bandwidth capability will be reduced.

17. DAC38RF80 Interpolation Options
One example of a DAC device from TI that has an internal interpolation function is the DAC38RF80. As shown in this slide, this function allows for several different interpolation factors. Other parts in this family actually have more options. This table also shows the user which filters are used to create the individual interpolation factor.

18. Sample Rate vs Data Rate with JESD204B Data Converters
Today’s JESD converters are sampling up to 9Gsps!
- 16 bit, JESD204B 8 lane DAC with Fs = 9Gsps, input data rate = 90Gbps per lane!
- Cannot be support by FPGA or ASIC’s
- Interpolation must be used to reduce the data rate
- This would meet JESD204B max data rate of 12.5Gbps
- ADC12J4000 with Fs = 4Gsps, output data rate = 80Gbps
- Decimation must be used if number of lanes is less than 8.
These next slides will discuss the sampling of newer high speed data converters that are using the JESD204B standard. JESD204B is a standardized serial interface between data converters and logic devices, such as FPGAs or ASICs, and is used by most of the new high speed data converters being developed today. With this new standard, JESD204B parts are easily sampling in the Giga Hertz range. Some of the newer RF DAC’s can sample up to 9Gsps. Sampling at this rate has its drawbacks as this would require input data rates in ranges up to 90Gbps per serdes lane. Since the JESD204B standard can only support rates up 12.5Gsps, the data rate must be lowered. To accomplish this, interpolation is used. Many of the JESD DAC’s have several options to chose from regarding the interpolation factor. This allows the user options when it comes to choosing how many serdes lanes they will need and how fast these will operate at. This is not as much a problem with current JESD204B ADC converters, as they are not sampling as fast, but if the user would like to reduce the number of lanes, then this becomes a problem and decimation would be required.

19. JESD204B DAC Example
DAC38J84: 16b Quad DAC with up to 8 lanes JESD204B up to 12.5Gbps/lane
Data rate = 2.5Gsps/DAC, 4 DACs = M = 4, Int 4x
Octet rate per DAC: 2 octets (16 bits) per sample. Fs = 2.5Gsps / 4 = 625Msps
625Msps*2 = 1250Moctets/sample/DAC
Bitrate per DAC: 8b/10b coding
1250Moctets/s*10bits/octet = 12,500Mbps
Total bit rate = 4 DACs * Gbps = 50Gbps (total through put)
If we choose L=8 lanes then the lane rate:
Lane rate = 50Gbps/8 = 6.25 Gbps per lane
LMFS=8411, lane rate = 6.25Gbps
In this example, we show a DAC38J84 that will use all four DAC’s, 8 serdes lanes, interpolation factor of 4, and a maximum DAC sample rate of 2.5Gbps.
To determine if the serdes rate will fall with the spec of the JERSD204B standard, we will do the following calculations:
1. First we will convert the octets used in JESD204B into bits. Since each sample comprises of 2 octets, there will be Megs octets per sample per DAC. JESD204B uses 8b/10b encoding, each octet will consist of 10 bits, so this then comes out to 12,500Mbps. Now the total bit rate is 12500Mbps times 4 DAC’s which is equal to 50Gbps. To get this below 12.5Gbps, we chose 8 serdes lanes, to bring this down to 6.25Gbps. Another option would be to use 4 lanes, which would have this at 12.5Gbps. This is were a customer would have a trade off to make. Use more lanes at a slower speed or less at a much higher rate. They could not use less than 4 lanes as this would exceed the serdes data rate of the JESD204 spec.

20. Min/Max Sample rates from the DAC38J84 Data Sheet
In this slide, you will see a table showing the minimum and maximum sample rates that can be used by this DAC. Fdata is the rate parallel data is leaving the JESD204B block and feeding the digital input block of the DAC. Fdac is the actual sample rate of the DAC. Fdac is equal to Fdata * the interpolation factor. Since the serdes outputs use an internal PLL, they will have a minimum as well as a maximum operating range. Due to this, JESD204B data converters have a relatively high minimum sample rate. In many cases, to use the maximum sample rate, the user must use some interpolation to get the serdes rate down below the 12.5Gbps that is the maximum allowed by the JESD204B standard.

21. Summary Sample rate and Data rate are not always the same frequency.
Decimation and Interpolation are used to reduce data rates to allow for much higher sampling rates.

22. Thanks for your time!
That concludes this video – thank you for watching!

23. © Copyright 2017 Texas Instruments Incorporated. All rights reserved.
This material is provided strictly “as-is,” for informational purposes only, and without any warranty.
Use of this material is subject to TI’s Terms of Use, viewable at TI.com