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Power MOSFET Pranjal Barman
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Power MOSFET • Introduction Advantages and Applications
Outline • Introduction Advantages and Applications Construction of power MOSFET • Physical operations of MOSFETs • Power MOSFET Characteristics • Factors limiting operating specifications of MOSFETs • Improved Designs • Future of power MOSFET
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Introduction A power MOSFET is a specific type of metal oxide semiconductor field-effect transistor designed to handle significant power levels. It was made possible by the evolution of CMOS technology, developed for manufacturing Integrated Circuits in the late 1970s. The power MOSFET shares its operating principle with its low-power counterpart, the lateral MOSFET.
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Advantages High speed switching High input impedance
High ON-state current handling capability High OFF-state blocking voltage Higher breakdown voltage
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Applications
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Construction of power VDMOSFET
Planar-gate structure P-base region and the N+ source regions are self-aligned to the edge of the polysilicon gate Thick N-drift region N+ substrate act as a drain
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Physics of MOSFET Insulator with finite resistivity
Charge only in the metal and semiconductor Work functions of metal and semiconductor are same
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Accumulation Excess minority carriers produced at the surface
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Depletion
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Inversion
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Total charge in semiconductor
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Charge,Field and Potential distribution
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Graded doping profile
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MOSFET characteristics
𝑉 𝑔𝑠 < 𝑉 𝑡ℎ ,cut off 𝑉 𝑔𝑠 - 𝑉 𝑡ℎ = 𝑉 𝑑𝑠 saturation 𝑉 𝑔𝑠 - 𝑉 𝑡ℎ < 𝑉 𝑑𝑠 ,pinch off K depends on temperature and device geometry
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Transconductance High transconductance is desirable to handle large current with low gate drive voltage Mobility degradation with temperature affect the transconductance Define the gain of the MOSFET
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Drift Velocity Saturation
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Effect of parasitic BJT
Transistor should not be turned on Shorted body and source A parasitic diode formed between source and drain
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Third quadrant operation
Current flow reverse direction compared to first quadrant No current saturation behavior observed Most common in DC-DC buck converters
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Field profile of VDMOSFET
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MOS capacitances Non linear and depends on device geometry
Gate-source capacitance Cgs approximately constant and independent of applied voltages. Gate-drain capacitance Cgd varies with applied voltage variation due to growth of depletion layer thickness until inversion layer is formed. Cds does not materially effect switching characteristics
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VDMOS capacitances
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Variation of capacitance with bias
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Factors limiting operating specifications
Maximum gate to source voltage MOSFET breakdown voltage MOSFET ON-state losses MOSFET Safe Operating Area (SOA)
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Maximum gate-source voltage
• VGS(max) = maximum permissible gate- source voltage. • If VGS >VGS(max) rupture of gate oxide by large electric fields possible. • EBD(oxide) ≈ 5-10 million V/cm • Gate oxide typically 1000 A thick • VGS(max) < 50 V • Typical VGS(max) V • Static charge on gate conductor can rupture gate oxide
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MOSFET breakdown Caused by avalanche breakdown of drain body junction
Larger value of breakdown could be achieved by Avoidance of drain-source reach-through by heavy doping of body and light doping of drain drift region Appropriate length of drain drift region Field plate action of gate conductor overlap of drain region Prevent turn-on of parasitic BJT with body-source short
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ON state loss On-state power dissipation 𝑃 𝑜𝑛 = 𝐼 𝐷 2 . 𝑅 𝑑𝑠 (on)
𝑅 𝑑𝑠 = 𝑅 𝑐𝑠 + 𝑅 𝑛+ + 𝑅 𝑐ℎ + 𝑅 𝑎 + 𝑅 𝑗𝑓𝑒𝑡 + 𝑅 𝑑 + 𝑅 𝑠𝑢𝑏 + 𝑅 𝑐𝑑 Large 𝑉 𝑔𝑠 minimizes accumulation layer resistance and channel resistance 𝑅 𝑑𝑠 (on) dominated by drain drift resistance for BVdss > few 100 V 𝑅 𝑑𝑠 (on) increases as temperature increses. Due to decrease in carrier mobility with increasing temperature.
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ON state resistances Channel resistance Accumulation resistance
JFET resistance Drift resistance Substrate resistance
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Safe Operating Area Three factors determine SOA
Maximum drain current Idm Internal junction temperature Tj which is governed by power dissipation Breakdown voltage BVdss
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Improved Design Approach
Reduce specific ON resistance Shorter channel length Improve input capacitance Higher reverse blocking capability
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UMOSFET Specific resistance is substantially small
Trench gate architecture Does not contain JFET region High input capacitance High gate transfer charge Complex fabrication process
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U-MOSFET with rounded trench and thicker oxide
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ON resistance
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Shielded Channel MOSFET
Shielding junction unique JFET region Reduced fabrication complexity Shorter channel length Reduced specific on resistance Reduced input capacitance Reduced gate transfer charge
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Shielded Channel MOSFET
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Charge Couple MOSFET Two dimensional charge coupling effect
Electrode embedded within oxide coated deep trenches Higher doping drift region Significantly smaller specific ON resistance Large input and gate transfer capacitance
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Charge Couple MOSFET
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CC-MOSFET with source electrode
Presence of the gate electrode within the deep trenches adjacent to the drift region increases the capacitance and gate charge degrading the switching performance of the power CC-MOSFET structure. This problem can be overcome by using a source connected electrode in the trenches adjacent to the drift region.
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CCMOS ON resistance No JFET resistance
Drift resistance is parallel to accumulation resistance
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Super Junction MOSFET Large blocking voltage capability upto 1200V
Alternating P and N type drift region Two dimensional charge coupling Highly doped drift reduce ON resistance
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Super Junction MOSFET
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ON resistance comparison
MOSFET Gate voltage=4.5V (mohm-cm2) Gate voltage=10V VDMOS 1.405 0.704 UMOS 0.613 0.176 SCMOS 0.235 0.202 CCMOS 0.380 0.017 SJMOS 0.911 0.839
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Wide Band Semiconductor
Si devices are limited to operate at junction temperature of 200 degree centigrade Si power devices not suitable for high frequency Lower specific on resistance of WB material SiC/GaN offer the potential to overcome the limitations of Si
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Silicon Carbide MOSFET
Specific ON resistance could be reduced by wide band gap semiconductor Quality of the interface between the thermally grown oxide and the SiC surface has been poor resulting in low inversion layer mobility High electric field within the gate oxide leading to its rupture during operation Two types of design approach-inversion and accumulation
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Silicon Carbide Inversion MOSFET
Larger threshold required to make inversion P-base doping should be very low to achieve small threshold High electric field rupture gate oxide Shielding allows to reduce channel length
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Inversion mode SiC-MOSFET
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SiC Accumulation MOSFET
A lightly doped N-base region used instead of P-base region Positive bias to the N-base region form accumulation region Prevent large electric field by P+ shielding Lower threshold voltage Shorter channel length
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Field pattern
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SiC-MOS Comparison Inversion Accumulation Higher Threshold
Low channel mobility High specific ON resistance Lower Threshold High channel mobility Low specific ON resistance
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Future of power MOSFET SiC MOS could outperform the blocking voltage upto 10000V IGBT favored due to low on-state voltage drop Very low specific on resistance with UMOSFET Silicon power integrated circuits
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References Advanced power MOSFET-J.Baliga
Power electronics converter application and design-N.Mohan Fundamental of power semiconductor device-J.Baliga Power MOSFETS basic-A.Sattar The future of power semiconductor device-J. Baliga
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Thank you
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