1. I/O techniques - Interfacing
Most topics discussed & experiments assigned in lab
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2. Overview I/O hardware I/O Software Three I/O mechanisms
ports, buses, devices, controllers
I/O Software
Interrupt Handlers, Device Driver, Device-Independent Software, User-Space I/O Software
Three I/O mechanisms
Polling, interrupt and DMAs
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3. I/O System I/O programming - abstracted by OS Device driver
USB
Driver
Dev
controller
Bus
LAN
Network
adapter
driver
SSD
drive
Device driver
Device controller
I/O programming - abstracted by OS
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4. Devices have different data Rates different I/O techniques used + sensors, actuators, SSD, router
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5. Morgan Kaufmann Publishers
27 October, 2017
I/O Basics
I/O controller  I/O devices ports
Transfers data to/from device
Synchronizes operations with software
Command / control registers
Status registers: device status, errors
Data registers
Write: data  device eg Transmit
Read: CPU device eg receive
multiple I/O registers can map to same address
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Chapter 6 — Storage and Other I/O Topics

6. Device Controller needed
I/O electro-mechanical
mechanical : device itself
electronic : device controller / adapter
Low level Interface between controller and device
Example: Disk controller
serial bit stream from drive  block of bytes, sector, track, error correction.
Character devices : input, serial port, sound, I2C
Block devices : USB storage, SSD, CD
Network devices : LAN or Wi-fi
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7. Device Drivers
Device-specific – controls IO device, written by manufacturer eg SSD driver, mouse,
command registers, commands vary from device to device
Part of kernel
Compiled with OS, Dynamically loaded into OS
Accept abstract R/W requests from device-independent layer ;
Initialize device, Manage power, and log
Check & translate input parameters
e.g., convert linear block number into the head, track, sector and cylinder number for disk access
Check device status & Control  sequence of commands
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8. CPU ­ Bus ­ I/O CPU needs to talk to I/O Memory­mapped I/O
Devices mapped to reserved memory locations - like RAM
Uses load/store instructions just like accesses to memory
I/O mapped I/O
Special bus line
Special instructions
Address
CPU
Memory
I/O Device
Data
Read
Write
Address
CPU
Data
Memory I/O
Read
Write
I/O Port
Memory
I/O Device
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9. Memory-Mapped I/O & I/O Mapped I/O
(a) Separate memory & I/O and space
(b) Memory-mapped I/O
(c) both
Most Popular
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10. I/O Register Mapping - summary
Morgan Kaufmann Publishers
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I/O Register Mapping - summary
Memory mapped I/O
Device Registers addressed similar to memory
OS - only accessible to kernel
OR I/O instructions
Separate instructions to access I/O
kernel mode
Example: x86
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Chapter 6 — Storage and Other I/O Topics

11. Embedded System Memory Map memory + I/O
Memory Space requirements
Flash memory application, kernel, boot, ..
DRAM
I/O reserved space for peripherals ..
BIOS f controls processor on powerup, Initialize hardware, memory subsystem
loads OS from drive
A.k.a bootloader .
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12. Parallel vs. Serial Digital Interfaces
Multiple parallel data lines
Hi Speed
Ex: PCI, ATA, CF cards
Serial convenient
minimal data lines
Low Power, length
Ex: USB, SATA, SD (secure digital), I2C, SPI, CAN, PCI-Express
categorize most physical connections today into either parallel or serial
ATA bus used in PCs
CF Compact flash cards
SATA, serial ATA bus
One of the most important issues in serial and parallel communication is synchronization
Parallel:
Speed - Faster because can transfer more bits?? However, there is the issue of cross talk and clock skew, limiting parallel ports
Simplicity - Simple in hardware, doesn’t require conversion back to serial, just requires a latch to send data to bus
Speed - Maybe?
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13. USB 2.0 - 3.0 universal serial bus – replace rs232
Speeds:
Up to 5Gb/s for 3.0
Older speed up to 480 Mb/s.
4 pins – (2.0), 9 pins (3.0)
Vbus, Gnd.
D+, D-
Male – Female connectors
Mini USB
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14. Example I/O :RS232 –Serial I/O Parallel to Serial –Lab, icreate
Required Blocks
Input – Output shift registers
Transmit (TX) Receive (RX) control
Read / write control
TX – RX buffers ;
FIFO
Clocking
Configuration needed
Baud rate
Number of bits (5-8)
Parity
Stop bits (1-2)
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15. UART for parrallel  serial
Universal Asynchronous Receiver Transmitter
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16. I/O eg: Minicom UART Serial I/O CPU interface
includes non-digital component.
Digital interface to CPU (control & status registers)
8251
status
(8 bit)
CPU
xmit/
rcv
data
(8 bit)
serial
port
8251
status
(8 bit)
CPU
xmit/
rcv
serial
port
data
(8 bit)
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17. 68HC11 Microcontroller UART
UART Registers
RSR Receive Shift Register
RDR Receive Data Register
TDR Transmit Data Register
TSR Transmit Shift Register
SCCR Serial Communications Control Register
SCSR Serial Communications Status Register
UART Flags
TDRE Transmit Data Register Empty
RDRF Receive Data Register Full
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18. UART Block Diagram - FYI
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19. UART: Universal Asynchronous Receiver-Transmitter - summary
Convert serial data to parallel data, and vise versa.
Uses shift registers to load store data
Can raise interrupt when data is ready
Commonly used with RS-232 interface
For serial data, the processor needs to read it in through the data bus, which is typically parallel, so you need a conversion back from serial to parallel.
It also helps synchronize the communication
Synchronize, interrupt the processor, buffer the data
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20. 3 I/O Data Transfer techniques
Morgan Kaufmann Publishers
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3 I/O Data Transfer techniques
Polling
interrupt-driven I/O
CPU transfers data between memory and I/O
Time consuming for high-speed devices
Direct memory access (DMA)
OS provides start info: memory address, control
DMA controller transfers to/from memory autonomously - direct
Controller interrupts on completion / error
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Chapter 6 — Storage and Other I/O Topics

21. I/O Mechanisms - Polling
Morgan Kaufmann Publishers
27 October, 2017
I/O Mechanisms - Polling
Periodically check I/O status
If device ready, do operation
If error, take action
small or low-performance real-time embedded systems
Predictable timing
Low hardware cost
wastes CPU time
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Chapter 6 — Storage and Other I/O Topics

22. I/O Mechanisms -Interrupts
Devices managed by interrupt controller  interrupt lines –
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23. Morgan Kaufmann Publishers
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Interrupts - review
When device ready or error
Interrupt  CPU, checked every instruction
CPU acknowledges interrupt ; saves the state
interrupt handler dispatched
determines cause, services the device and clears the interrupt
Context switch time
Priority interrupts
higher priority devices get more attention
Can interrupt lower priority device
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Chapter 6 — Storage and Other I/O Topics

24. I/O Mechanisms Direct Memory Access (DMA)
DMA transfer Operation
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25. Direct Memory Access (DMA)
Data Xfer: I/O device  Mem OR I/O  Mem
CPU assists & initiates Xfer
getting data from I/O controller to CPU on byte – basis inefficient – (e.g. disk data transfer)
Instead special purpose  DMA controller
Faster , more efficient
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26. DMA-CPU Protocol eg. DISK read
CPU programs DMA controller: - setup
specify source / destination addresses
byte count and control information (e.g., read/write)
DMA controller: Acknowledge - Xfer
Starts Xfer directly without CPU help
Request I/O controller to move data to memory
Disk controller data  main memory
Disk controller acks transfer complete to DMA controller
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27. DMA cont’d Handshaking between DMA controller and device controller
Cycle stealing
DMA controller steals bus cycles from CPU – blocks CPU from accessing memory
DMA improves system performance
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28. Choosing I/O method fastest for a single I/O request?
Programmed I/O
Interrupt-driven I/O
I/O using DMA
fastest for a single I/O request?
highest throughput?
Examples of use from each group
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29. I/O Buffer - smoothes speed mismatch
Buffer:: memory area buffers data between device and application.
Reasons of buffering:
speed mismatch between producer and consumer of data stream - use double buffering
Devices have different data-transfer sizes
application writes to buffer; OS copies to kernel buffer and disk.
Unbufferred input strategy ineffective
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30. I/O Errors must be Reported
Actual IO Errors
at device level (e.g., damaged disk block, switched off camera )
IO Programming Errors
e.g., write to keyboard, read from printer).
device-independent IO software detects / responds to errors; report  user-space IO software.
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