1. Next Generation Carbon Nanotube Based Electronic Design

2. Outline 2 1 Introduction 2 Carbon Nanotubes (CNT) Interconnect
Buffering CNT Interconnect for Timing Optimization 3 4
Preliminary Results for CNT Buffering 5
Fabrication Variation Aware CNT Buffering 2

3. Interconnect Delay Dominates
Copper 3

4. Bottleneck of Prevailing Copper Technology
Copper interconnect technology has its fundamental physical limit, interconnect delay due to ever increasing wire resistivity has greatly limited the circuit miniaturization. 4

5. Copper Global Interconnect Delay
Driver
Load
Technology node (nm)
Minimum pitch (nm) 68
210 52
156 40
120 32 96 22 66 18 54 14 42
Interconnect RC delay (ps) for a 1 mm length minimum pitch Cu global wire (ITRS 2007) 5

6. Carbon Nanomaterial Graphenes CNT 6
Carbon Nanotube (CNT) is one of the material of carbon as well as Graphenes.
Graphenes
CNT 6

7. Nobel Prize
The Nobel Prize in Physics 2010 was awarded jointly to Andre Geim and Konstantin Novoselov “
for groundbreaking experiments regarding the two-dimensional material graphene" 7

8. SWCNTs: Single-Walled Carbon Nanotubes
Single-walled carbon nanotube (SWCNT) can be envisioned as a rolled up graphene sheet into a seamless cylinder with fullerene caps.
Diameters of SWCNTs are typically 0.5 to 3nm.
CNT lengths range from less than 100 nm to several centimeters 8

9. Bundled SWCNTs
1nm
0.32nm
Bundled SWCNTs consist of a bundle of parallel single SWCNTs 9

10. Mean Free Path of CNT 10 40nm 1000nm
All particles suffer from collisions with other particles such that their path through space is very short for high densities. This typical path length is called the mean free path.
The longer mean free path results in smaller resistivity.
Resistivity 𝜌∝ 1 𝑙 10

11. Advantage of CNT Compared to Cu
Properties
CNT Cu
Mean Free Path
1000𝑛𝑚
40𝑛𝑚
Max. Current Density
10 10 𝐴/ 𝑐𝑚 2
10 6 𝐴/ 𝑐𝑚 2
Thermal Conductivity
6000𝑊/𝑚𝐾
400𝑊/𝑚𝐾
Copper interconnect technology is approaching its fundamental physical limit, and issues such as electromigration and ever increasing wire resistivity which has greatly limited the circuit miniaturization.
Carbon nanotube (CNT) interconnect is a promising replacement material. CNT has better performance in mean free path, maximum current density and thermal conductivity. 11

12. CNT Fabrication Process: Chemical Vapor Deposition (CVD)
Among several techniques of CNT synthesis available
today, chemical vapor deposition (CVD) is most popular
and widely used because of its low set-up cost, high
production yield, and ease of scale-up.
CVD uses carbon precursors from gas phase to form CNTs that takes place at relatively low temperatures (500–1000 °C), providing great scalability and controllability. Thus, CVD is regarded as a highly promising CNT growth
technique for the purpose of large-scale synthesis 12

13. Quartz Wafer-Scale Aligned CNT Growth
Quartz wafer with catalyst 13

14. Transfer CNTs from Quartz Wafers to Silicon Wafers
CNT transfer technique using Thermal Release Tape.
SEM of CNTs on quartz.
100 nm of Au evaporated on 4” quartz wafer after CNT growth.
Thermal release tape is applied to the Au film and the tape/Au bilayer is peeled off.
SiO2/Si Wafer with transferred Au after tape release at 120oC.
SEM images of SWNTs transferred from quartz to 50 nm SiO2 on Si after gold etching (KI/I2).
(f) Si wafer after substrate-gated CNFET fabrication.
Scanning electron microscope
N. Patil, A. Lin, E. Myers, H.-S. P.Wong, and S. Mitra, “Integrated waferscale growth and transfer of directional carbon nanotubes and misalignedcarbon-nanotube-immune logic structures,” in Proc. Symp. VLSI Technol., pp. 205–206, 2008. 14

15. CNT Fabrication Orientation Control
Surface structures of substrate and state of gas flow can partially decide the growth orientation of SWCNTs under a suitable temperature range 15

16. CNT Fabrication Length Control
To selectively grow SWCNT arrays with certain length, one easy way is confining the spatial termination position of growing SWCNTs, which means to obstruct the growth of SWCNTs by instantaneously stopping the catalysts' activity possibility with additional barriers at a certain position.
Rogers et al. introduce a layer of amorphous SiO2 onto quartz surface, and SWCNTs terminated at the edge of the SiO2 layer because of the surface relief 16

17. CNT Fabrication Density Control
Keeping catalyst activity; multiple-cycle CVD growth; adding in new catalysts to grow new SWCNTs 17

18. CNT Variations in Density
Aligned arrays of CNTs can take full advantage of
the superior transport characteristics of CNTs, and therefore are considered to be most suitable for high-performance circuit applications.
The density of variations will impact on the resistance and capacitance parameters of bundled CNTs 18

19. CNT Fabrication Diameter Control
Depend on the diameter of catalysts and Temperature 19

20. CNT Variation in Diameter 20

21. Mis-alignment CNT
State-of-the-art CNT growth techniques today are able to produce CNTs with >99.9% alignment for low density.
A mis-positioned CNT is a CNT that passes through a layout region where it is not intended to pass. Mis-positioned CNTs can cause reduced drive current and even incorrect logic functionality.
In our design, high density CNTs are desired and mis-alignment becomes an important issue. 21

22. Outline 22 1 Introduction 2 Carbon Nanotubes (CNT) Interconnect
Buffering CNT Interconnect for Timing Optimization 3 4
Preliminary Results for CNT Buffering 5
Fabrication Variation Aware CNT Buffering 22

23. Overview of Bundled SWCNTs Circuit Model
Bundled SWCNTs interconnect
Driver
Load
𝑅 𝑑𝑟
𝐶 𝑑𝑟
𝑅 𝑐_𝑢𝑝
𝐶 𝑙𝑜𝑎𝑑
𝑅 𝑐_𝑑𝑜𝑤𝑛
𝐶𝐸 𝑏𝑢𝑛𝑑𝑙𝑒 ∙𝑙 2
𝑅𝑄 𝑏𝑢𝑛𝑑𝑙𝑒 2
𝑅 𝑆 𝑏𝑢𝑛𝑑𝑙𝑒 𝑙 23

24. Quantum Resistance of Single SWCNT
If the size of the structure is of the same scale as the mean free path of an electron, Ohm’s law may not apply, there exist quantum effects
Quantum resistance (the lowest possible resistance of an isolated SWCNT)
𝑅 𝑄 = ℎ 4 𝑒 2 =6.45𝑘Ω
ℎ=6.626×10−34 J·s -- Plank’s constant
𝑒=1.602×10−19 Coulombs -- the electronic charge 24

25. Scattering Resistance of Single SWCNT
Scattering unit resistance
𝑅 𝑆 = ℎ 4 𝑒 2 𝜆 =6.45𝑘Ω/𝜇𝑚, when 𝑙>λ
For simplicity, define 𝑅 𝑆 =0, when 𝑙≤λ
Total resistance of a single SWCNT
𝑅 𝑖𝑠𝑜𝑙𝑎𝑡𝑒𝑑 = 𝑅 𝑄 + 𝑅 𝑆 𝑙
ℎ=6.626×10−34 J·s -- Plank’s constant
𝑒=1.602×10−19 Coulombs -- the electronic charge
𝜆 is the mean free path of electrons for a CNT
𝑙 is the length of CNT 25

26. Resistance of Bundled SWCNTs
Total resistance of bundled SWCNTs
𝑅 𝑏𝑢𝑛𝑑𝑙𝑒 = 𝑅 𝑖𝑠𝑜𝑙𝑎𝑡𝑒𝑑 / 𝑁 𝑐𝑛𝑡
𝑅 𝑖𝑠𝑜𝑙𝑎𝑡𝑒𝑑 is total resistance of a single SWCNT
𝑁 𝑐𝑛𝑡 is the number of SWCNTs contained in the bundle
For global interconnect, the scattering resistance dominates, thus,
𝑅 𝑏𝑢𝑛𝑑𝑙𝑒 = 𝑅 𝑖𝑠𝑜𝑙𝑎𝑡𝑒𝑑 / 𝑁 𝑐𝑛𝑡 = 𝑅 𝑆 𝑙/ 𝑁 𝑐𝑛𝑡 26

27. Contact Resistance
Imperfect contacts between copper and carbon nanotubes
CNT interconnect layer
Contact resistance
Some research groups have accomplished to fabricate the contact resistances ranging from a few hundred ohms to a few kilohms 27

28. Quantum Capacitance of Single SWCNT and Bundled SWCNTs
Quantum unit capacitance
𝐶 𝑄 = 2 𝑒 2 ℎ 𝑣 𝑓
where 𝑣𝑓 is the Fermi velocity (𝑣𝑓 ≈ 8 ×105 𝑚/𝑠)
Since an SWCNT has four conducting channels, the net quantum capacitance of a single SWCNT is
𝐶 𝑄 𝐶𝑁𝑇 =4𝐶 𝑄
Quantum capacitance of a bundled SWCNTs is
𝐶 𝑄 𝑏𝑢𝑛𝑑𝑙𝑒 = 𝑁 𝑐𝑛𝑡 𝐶 𝑄 𝐶𝑁𝑇 28

29. Electrostatic Capacitance of Single SWCNT and Bundled SWCNTs
Electrostatic unit capacitance
𝐶 𝐸 = 2𝜋𝜖 𝑐𝑜𝑠ℎ −1 (𝑦/𝑑)
FastCap is used to calculate the electrostatic capacitance of each single SWCNT 29

30. Effective Capacitance of Bundled SWCNTs
The effective capacitance of an SWCNT bundle interconnect (Cbundle) is given by the series combination of its electrostatic capacitance and quantum capacitance.
As shown in left figure, the effective SWCNT bundle capacitance is nearly equal to its electrostatic capacitance and the effect of the quantum capacitance is small.
N. Srivastava, H. Li, F. Kreupl and K. Banerjee, “On the Applicability of Single-Walled Carbon Nanotubes as VLSI Interconnects,” IEEE Transactions on Nanotechnology, vol. 8, no. 4, pp. 542–559, 2009. 30

31. Inductance of Single SWCNT and Bundled SWCNTs
Kinetic inductance of single SWCNT
𝐿 𝐾 𝑖𝑠𝑜𝑙𝑎𝑡𝑒𝑑 = ℎ 8 𝑒 2 𝑣 𝐹
Magnetic inductance of single SWCNT 𝐿 𝑀 𝑖𝑠𝑜𝑙𝑎𝑡𝑒𝑑 = 𝜇 2𝜋 𝑐𝑜𝑠ℎ −1 ( 𝑦 𝑑 )
Inductance of bundled SWCNTs
𝐿 𝑏𝑢𝑛𝑑𝑙𝑒 = 𝐿 𝐾 𝑖𝑠𝑜𝑙𝑎𝑡𝑒𝑑 + 𝐿 𝑀 𝑖𝑠𝑜𝑙𝑎𝑡𝑒𝑑 𝑁 𝑐𝑛𝑡 31

32. Inductive Effect of Bundle SWCNTs is Not Important
𝑅 𝑑𝑟 𝐶𝑙< 1 2 𝑅𝑙𝐶𝑙< 𝐿𝐶 𝑙
where Rdr is the driver impedance and R, C and L are the per unit length interconnect resistance, capacitance and inductance.
𝑅 𝑑𝑟 𝐶𝑙
𝐿𝐶 𝑙
(1/2)𝑅𝑙𝐶𝑙
The above inequality never holds, inductance can be ignored.
N. Srivastava, H. Li, F. Kreupl and K. Banerjee, “On the Applicability of Single-Walled Carbon Nanotubes as VLSI Interconnects,” IEEE Transactions on Nanotechnology, vol. 8, no. 4, pp. 542–559, 2009. 32

33. Bundled SWCNTs Interconnect Model
CNT interconnect layer
Bundled SWCNTs interconnect
Driver
Load
𝑅 𝑑𝑟
𝑅 𝑐,𝑑𝑜𝑤𝑛𝑠𝑡𝑟𝑒𝑎𝑚
𝑅𝑄 𝑏𝑢𝑛𝑑𝑙𝑒 2
𝐶 𝑄 𝑏𝑢𝑛𝑑𝑙𝑒
𝐶 𝑙𝑜𝑎𝑑
𝑅 𝑐,𝑢𝑝𝑠𝑡𝑟𝑒𝑎𝑚
𝐶 𝐸 𝑏𝑢𝑛𝑑𝑙𝑒
𝑅𝑆 𝑏𝑢𝑛𝑑𝑙𝑒 33

34. Bundled SWCNT Interconnect π Model
𝑅 𝑑𝑟
𝐶 𝑑𝑟
𝑅 𝑐,𝑑𝑜𝑤𝑛𝑠𝑡𝑟𝑒𝑎𝑚
𝐶 𝑙𝑜𝑎𝑑
𝑅 𝑐,𝑢𝑝𝑠𝑡𝑟𝑒𝑎𝑚
𝐶𝑄 𝑏𝑢𝑛𝑑𝑙𝑒 ∙ 𝐶𝐸 𝑏𝑢𝑛𝑑𝑙𝑒 ∙𝑙 2( 𝐶𝑄 𝑏𝑢𝑛𝑑𝑙𝑒 + 𝐶𝐸 𝑏𝑢𝑛𝑑𝑙𝑒 )
𝑅𝑄 𝑏𝑢𝑛𝑑𝑙𝑒 + 𝑅𝑆 𝑏𝑢𝑛𝑑𝑙𝑒 𝑙 34

35. Bundled SWCNT Global Interconnect Simplified π Model
𝑅 𝑑𝑟
𝐶 𝑑𝑟
𝑅 𝑐,𝑑𝑜𝑤𝑛𝑠𝑡𝑟𝑒𝑎𝑚
𝐶 𝑙𝑜𝑎𝑑
𝑅 𝑐,𝑢𝑝𝑠𝑡𝑟𝑒𝑎𝑚
𝑅 𝑆 𝑏𝑢𝑛𝑑𝑙𝑒 𝑙
𝐶𝐸 𝑏𝑢𝑛𝑑𝑙𝑒 ∙𝑙 2 35

36. Outline 36 1 Introduction 2 Carbon Nanotubes (CNT) Interconnect
Buffering CNT Interconnect for Timing Optimization 3 4
Preliminary Results for CNT Buffering 5
Fabrication Variation Aware CNT Buffering 36

37. Delay = all Ri all Cj downstream from Ri Ri*Cj
Delay for A Circuit
Delay = all Ri all Cj downstream from Ri Ri*Cj
Elmore delay to n1 R(B)*(C1+C2)
Elmore delay to n2 R(B)*(C1+C2)+R(w)*C2 37

38. Buffer Insertion For Delay Reduction38

39. Why Buffers Can Reduce Delay?
(Rd,Cd)
(CL)
(Rd,Cd)
(Rb,Cb)
(CL)
𝑅 𝑑 𝑟𝑙
𝑅 𝑑
𝑟𝑙/2
𝑅 𝑏
𝑟𝑙/2
𝑐𝑙 2
𝑐𝑙 2
𝑐𝑙 4
𝑐𝑙 4
𝑐𝑙 4
𝑐𝑙 4
𝐶 𝑑
𝐶 𝐿
𝐶 𝑑
𝐶 𝑏
𝐶 𝐿
𝑡 𝑢𝑛𝑏𝑢𝑓 = 𝑅 𝑑 𝑐𝑙+ 𝐶 𝐿 +𝑟𝑙( 𝑐𝑙 2 + 𝐶 𝐿 )
𝑡 𝑏𝑢𝑓 = 𝑅 𝑑 𝑐𝑙 2 + 𝐶 𝑏 + 𝑟𝑙 2 𝑐𝑙 4 + 𝐶 𝑏 + 𝑅 𝑏 𝑐𝑙 2 + 𝐶 𝐿 + 𝑟𝑙 2 ( 𝑐𝑙 4 + 𝐶 𝐿 ) 𝑙 ∆𝑡
Suppose that 𝑅 𝑑 = 𝑅 𝑏 , 𝐶 𝑑 = 𝐶 𝑏
∆𝑡= 𝑡 𝑏𝑢𝑓 − 𝑡 𝑢𝑛𝑏𝑢𝑓 = 𝑅 𝑏 𝐶 𝑏 −𝑟𝑐 𝑙 2 /4 39

40. CNT Buffering and Copper Buffering
CNT interconnect layer
Copper interconnect layer
Copper buffering
CNT buffering 40

41. Existing Works
Some existing works consider the CNT interconnect or buffered CNT interconnect, however, they only use a two pin mode interconnect model
None of the existing works consider the deployment of CNT into VLSI physical design
N. Srivastava, H. Li, F. Kreupl and K. Banerjee, “On the Applicability of Single-Walled Carbon Nanotubes as VLSI Interconnects,” IEEE Transactions on Nanotechnology, vol. 8, no. 4, pp. 542–559, 2009.
A. Nieuwoudt and Y. Massoud, “On the optimal design, performance, and reliability of future carbon nanotube-based interconnect solutions,” IEEE Transactions on Electron Devices, vol. 55, no. 8, pp. 2097–2110, 2008.
G. Close and H.-S. Wong, “Assembly and electrical characterization of multiwall carbon nanotube interconnects,” IEEE Transactions on Nanotechnology, 2008.
A. Naeemi and J. D. Meindl, “Design and performance modeling for singlewall carbon nanotubes as local, semi-global, and global interconnects in gigascale integrated systems,” IEEE Transactions on Electron Devices, vol. 54, no. 1, pp. 26–37, 2008. 41

42. Problem Formulation
Timing Constrained Minimum Cost Buffering for Carbon Nanotube Interconnects:
Given a binary routing tree with 𝑛 candidate buffer locations in carbon nanotube interconnect layer, a buffer library and a set of candidate buffer positions, to compute a buffer assignment solution such that the timing constraint is satisfied, and the total buffer cost is minimized. 42

43. Solution Characterization
To model effect to downstream, a candidate solution is associated with
v: a node
C: downstream capacitance
Q: required arrival time
W: cumulative buffer cost 43

44. Candidate Buffering Solutions44

45. Dynamic Programming (DP)
Start from sinks
Candidate solutions are generated
Three operations
Add Wire
Insert Buffer
Merge
Solution Pruning
Candidate solutions are propagated toward the source 45

46. Solution Propagation: Add Buffer
(𝑄 𝛾 ′ ,𝐶 𝛾 ′ ,𝑊 𝛾 ′ )
(𝑄 𝛾 ,𝐶 𝛾 ,𝑊(𝛾)) 46

47. Solution Propagation: Add Wire
(𝑄 𝛾 𝑣 ,𝐶 𝛾 𝑣 ,𝑊 𝛾 𝑣 ) 𝑢 𝑣
𝑅 𝑢,𝑣 , 𝐶(𝑢,𝑣)
(𝑄 𝛾 𝑢 ,𝐶 𝛾 𝑢 ,𝑊 𝛾 𝑢 ) 47

48. Solution Propagation: Add Driver
(𝑄 𝛾 ,𝐶 𝛾 ,𝑊(𝛾))
(𝑄 𝛾 ′ ,𝐶 𝛾 ′ ,𝑊 𝛾 ′ ) 48

49. Branch Merge 49 (𝑄 𝛾 ,𝐶 𝛾 ,𝑊(𝛾)) (𝑄 𝛾 1 ,𝐶 𝛾 1 ,𝑊 𝛾 1 )
(𝑄 𝛾 1 ,𝐶 𝛾 1 ,𝑊 𝛾 1 )
(𝑄 𝛾 2 ,𝐶 𝛾 2 ,𝑊 𝛾 2 ) 49

50. Exponential Runtime 50 16 solutions 8 solutions 4 solutions
n candidate buffer locations lead to 2n solutions 50

51. Needs solution pruning for acceleration Two candidate solutions
Too Many Solutions
Needs solution pruning for acceleration
Two candidate solutions
(v, c1, q1,w1)
(v, c2, q2,w2)
Solution 1 is inferior to Solution 2 if
c1  c2 : larger load
and q1  q2 : tighter timing
and w1 w2: larger cost 51

52. Pruning 52 (Q1,C1,W1) inferior/dominated
if C1  C2,W1  W2 and Q1  Q2
(Q2,C2,W2) 52

53. Outline 53 1 Introduction 2 Carbon Nanotubes (CNT) Interconnect
Buffering CNT Interconnect for Timing Optimization 3 4
Preliminary Results for CNT Buffering 5
Fabrication Variation Aware CNT Buffering 53

54. Experimental Environment
The proposed carbon nanotube interconnect based timing driven minimum cost buffer insertion algorithm is implemented in C and tested on a machine with 3.40GHz Intel Pentium CPU and 3GB memory.
Simulation 1: Timing constrained minimum cost buffering
Simulation 2: Timing minimization without considering cost 54

55. Experimental Setup – Layer RC InformationCu
Bundled SWCNT (1000 SWCNTs)
Resistance (Ω)
14.50
6.45
Capacitance (fF)
0.16
𝑅 𝑐𝑢 = 𝜌𝑙 𝐴
CNT density = 1000/(33×88)=0.34 𝑛𝑚 2
Contact resistance is set to 100Ω 55

56. Experimental Setup – Buffer Library
Property
BUF_X1
BUF_X2
BUF_X4
BUF_X8
BUF_X16
Resistance (Ω)
2310.0
1201.0
618.9
315.5
159.6
Capacitance (fF)
0.21
0.44
0.88
1.76
3.51
Intrinsic delay (ps)
2.93
2.91
2.87
Area (nm2)
INV_X1
INV_X2
INV_X4
INV_X8
INV_X16
1846.0
976.5
514.8
270.2
139.7
0.87
1.74
3.49
6.97
0.59
0.62
0.61
Linear fitting 56

57. Experimental Setup – Global Nets
Our experiments are performed to 500 global nets.
Due to the lack of industrial nets in 22nm technology, we scale wire lengths of old technology nets to 22nm technology. 57

58. Experiment 1 Timing constrained minimum cost buffering
Timing minimization without considering cost 58

59. Experiment 1 Results of 500 Nets On Average (Normalized)59

60. Experiment 1 Results on Five Representative Nets
Test cases 1 2 3 4 5
Average
CNT w/o contact resistance
Area (nm2)
# Buffers 7 9
5.2
Delays (ps)
754
1128
676
1019
722
859.8
CNT w/ contact resistance (100Ω)
5.4
762
1130
691
927
736
849.2 Cu 18 19 12 10
15.0
766
1180
702
994
870
902.4 60

61. Area and Delay Trade-off Curves for Cu and CNT61

62. Experiment 2 Timing constrained minimum cost buffering
Timing minimization without considering cost 62

63. Experiment 2 Results on Five Representative Nets
Test cases 1 2 3 4 5
Average
CNT w/o contact resistance
Area (nm2)
# Buffers 50 61 44 32
46.0
Delays (ps)
376
724
314
249
188
370.2
CNT w/ contact resistance (100Ω) 36 31 24 18
30.8
423
797
347
302
229
419.6 Cu 65 67 56 48
59.4
479
877
382
363
276
475.4 63

64. Observations
In order to achieve the similar delay, the CNT buffering saves more than 50% buffer area over copper buffering
The total number of buffers in CNT buffering is much (about 2X) smaller than that of copper buffering thanks to the fact that wire resistivity of bundled SWCNTs is much lower than that of copper for global interconnect
The contact resistance does not have significant impact on the performance for CNT interconnect timing constrained minimum cost buffering
CNT buffering always outperforms the copper buffering in terms of timing and buffer area
CNT buffering can reduce timing by up to 32% comparing to copper buffering for buffering timing minimization without considering cost 64

65. Summary of CNT Buffering
Carbon nanotube interconnects have become a promising replacement material for copper interconnects thanks to their superior conductivity.
This work develops the first timing driven buffer insertion technique for carbon nanotube interconnects.
In the experimental results, it demonstrates that with the same timing constraint, CNT buffering can save over 50% buffer area compared to copper buffering. In addition, CNT buffering can effectively reduce the delay by up to 32% without considering cost.
This work is published in ISVLSI2014.
Lin Liu, Yuchen Zhou and Shiyan Hu, “Buffering Single Walled Carbon Nanotube Bundle Interconnects for Timing Optimization”, to appear in Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2014. 65

66. Outline 66 1 Introduction 2 Carbon Nanotubes (CNT) Interconnect
Buffering CNT Interconnect for Timing Optimization 3 4
Preliminary Results for CNT Buffering 5
Fabrication Variation Aware CNT Buffering 66

67. Fabrication Imperfectness
It is very difficult for today’s CNT processing to produce perfect CNTs.
New design techniques must be employed that are immune to these inherent CNT imperfections.
These new design techniques must be compatible with VLSI processing, and must have minimal impact on existing VLSI design flows. 67

68. Existing Works
Some research works studied the variations of CNT and some proposed robust design considering CNFET
Some research works studied the copper variation based buffer insetion
Jie Zhang, et al, "Carbon Nanotube Robust Digital VLSI," Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on , vol.31, no.4, pp.453,471, April 2012
Patil, N.; Lin, A.; Myers, E.R.; Ryu, Koungmin; Badmaev, A.; Chongwu Zhou; Wong, H. -S P; Mitra, S, "Wafer-Scale Growth and Transfer of Aligned Single-Walled Carbon Nanotubes," Nanotechnology, IEEE Transactions on , vol.8, no.4, pp.498,504, July 2009
Jie Zhang; Patil, N.P.; Hazeghi, A.; Wong, H. -S P; Mitra, S, "Characterization and Design of Logic Circuits in the Presence of Carbon Nanotube Density Variations," Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on , vol.30, no.8, pp.1103,1113, Aug. 2011
Raychowdhury, A.; De, V.K.; Kurtin, Juanita; Borkar, S.Y.; Roy, K.; Keshavarzi, A., "Variation Tolerance in a Multichannel Carbon-Nanotube Transistor for High-Speed Digital Circuits," Electron Devices, IEEE Transactions on , vol.56, no.3, pp.383,392, March 2009
Jinjun Xiong; Lei He, "Probabilistic Transitive-Closure Ordering and Its Application on Variational Buffer Insertion," Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on , vol.26, no.4, pp.739,742, April 2007 68

69. CNT Fabrication Variations
Distribution
CNT diameter variations (d)
Normal
𝜇 𝑑 =1.3𝑛𝑚
𝜎 𝑑 =0.2𝑛𝑚
CNT length variations (l)
𝜇 𝑙
𝜎 𝑙 = 𝜇 𝑙 cos 10 °
CNT counts (Ncnt)
𝜇 𝑁𝑐𝑛𝑡 =1000
𝜎 𝑁𝑐𝑛𝑡 =22
CNT distance to ground (y)
𝜇 𝑦
𝜎 𝑦 =0.1𝑛𝑚
Jie Zhang; Patil, N.P.; Hazeghi, A.; Wong, H. -S P; Mitra, S, "Characterization and Design of Logic Circuits in the Presence of Carbon Nanotube Density Variations," Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on , vol.30, no.8, pp.1103,1113, Aug. 2011 71

70. Parameters Variations
𝑅 𝑑𝑟
𝐶 𝑑𝑟
𝑅 𝑐,𝑑𝑜𝑤𝑛𝑠𝑡𝑟𝑒𝑎𝑚
𝐶 𝑙𝑜𝑎𝑑
𝑅 𝑐,𝑢𝑝𝑠𝑡𝑟𝑒𝑎𝑚
𝑅 𝑆 𝑏𝑢𝑛𝑑𝑙𝑒 𝑙
𝐶𝐸 𝑏𝑢𝑛𝑑𝑙𝑒 ∙𝑙 2
𝑙, 𝑁 𝑐𝑛𝑡 , 𝑦 and 𝑑 follow normal distribution
In a SWCNT bundle that contains large amount of CNTs
in parallel; according to Central Limit Theorem, we have
𝑅 𝑆 𝑏𝑢𝑛𝑑𝑙𝑒 ~𝑁 𝜇 𝑅 𝑆 𝑏𝑢𝑛𝑑𝑙𝑒 , 𝜎 𝑅 𝑆 𝑏𝑢𝑛𝑑𝑙𝑒 2
𝐶 𝐸 ~𝑁( 𝜇 𝐶 𝐸 , 𝜎 𝐶 𝐸 2 ) 70

71. Variation Aware Design
According to the distribution of each variable, generate large amount of test cases with deterministic values;
For each deterministic test case, perform the deterministic algorithm;
If the yield rate is large enough, the current solution is return; else generate new test cases and repeat 2. 71

72. Variation Aware Design on CNT Buffering Algorithm
Given the maximum and minimum of each variable
Generation the value of the variables by
𝑉=𝛽𝑉𝑚𝑎𝑥+(1−𝛽)𝑉𝑚𝑖𝑛, 𝛽 is initialized to 0
Generate large amount of test cases given normal distribution of each variables
Run the deterministic CNT buffering algorithm
Timing constraints yield rate is satisfied No
Update 𝛽=𝛽+∆
Yes
Return the buffering solution 72