The USBpix3 Readout System

The USBpix3 Readout System
ATLAS Upgrade Week 7th April 2014 Viacheslav Filimonov, Tomasz Hemperek, Fabian Hügging, Hans Krüger and Norbert Wermes

USBpix  ATLAS Pixel FE Chip Test System
7 Apr '14 USBpix  ATLAS Pixel FE Chip Test System BURN-IN Card: 4 individual channels Quad Module BURN-IN Card General Purpose Analog Card: 4 individual power supply channels 12 current sources 4 voltage sources CMOS IOs LVDS IOs 4 channel ADC Injection Pulse generator Currently I’m working on the upgrade of the USBpix test system. USBpix was developed as a small and light weighting test system for ATLAS FE-I3 pixel readout chips. Now it provides the functionality which is needed for a full characterization of FE-I4 pixel readout chips. Here you can see one variant of USBpix system. The USBpix hardware is built up in a modular way. It consists of three different PCB boards: S3 Multi IO Board Adapter Card Single Chip Card (CLICK) The S3 Multi IO Board is the central control unit of the test system containing all of the programmable hardware parts. It includes a free programmable Xilinx Spartan3 FPGA, SRAM Memory, USB2.0 Interface and an 8051 microcontroller with I2C and SPI functionality. The Adapter Card provides the necessary voltage for the Single Chip Card and holds level shifters, power supplies and diagnostic circuits. The Single Chip Card holds the FE-I4 chip. As I already mentioned, this is just one variant of USBpix system. (CLICK) Another variant replaces FE-I4 adapter card with Burn-in card. Burn-in card is also connected to MultiIO board via KEL connector. It has 4 individual channels for Quad Module readout. (CLICK) FE-I4 adapter card can also be replaced with general purpose analog card. It holds 4 individual power supply channels, 12 current sources, 4 voltage sources, CMOS IOs, LVDS IOs, 4 channel ADC , Injection Pulse generator and other components. It can be used for readout of various FE chips, for example, CCPD on FE-I4. FE-I4 + CCPD USBpix system for FE-I4 single chip read-out GPA Card Viacheslav Filimonov | The USBpix3 Readout System

Viacheslav Filimonov | The USBpix3 Readout System
7 Apr '14 MultiIO  SuperIO: USBpix upgrade motivation Resources on the MultiIO board are coming to their limits Current system developed mainly for single FE chip support → Simultaneous R/O of few chips (quad modules) and support of new chip generations with higher data rates becomes challenging Example: 4 FE-I4 160 Mbit/s = 80 Mbyte/s (USBpix to PC -> 15Mbyte/s) Requirements of a new FPGA card: Downward compatible to USBpix adapter cards and SW More data processing resources  Larger FPGA and memory Support of high speed I/O (Gbit serial links) Higher data bandwidth → USB 3.0 (Super Speed; > 150 Mbyte/s) Unfortunately, resources on the MultiIO board are coming to their limits. Current system was developed mainly for single FE chip support . That’s why it’s hard to r/o few chips (for example, quad modules) simultaneously and to support new chip generations with higher data rates. For example, 4 FE-I4 chips at continuous readout will result in 80 Mbyte/s data rate. And current USBpix system is only capable of 15 Mbyte/s data rate. That’s why it’s necessary to upgrade the MultiIO board. Upgraded MultiIO board should be downward compatible to USBpix adapter cards and SW, should have more data processing resources, that is larger FPGA (half the power consumption of previous Spartan families, and faster) and memory, should support high speed I/Os and should have higher data bandwidth, that is USB 3.0 interface. USB 3.0 interface is capable of data rates higher than 150 Mbyte/s, that is x10 improvement compared to current USBpix system. Viacheslav Filimonov | The USBpix3 Readout System

7 Apr '14 MultiIO  SuperIO: Selected upgrade option Commercial board Custom made carrier PCB Downward compatibility to existing USBpix adapter cards USB 3.0 connector KEL connector Functionality for FE chip characterization Other components One of the possible upgrade options was to use a commercial board with a custom made carrier PCB. Carrier PCB provides downward compatibility to existing USBpix adapter cards. It holds USB 3.0 connector and KEL connector specifically for that reason. It also holds a number of other components that provide functionality that is necessary for FE chip characterisation. Later I’ll give more details about them. Viacheslav Filimonov | The USBpix3 Readout System

7 Apr '14 Commercial board Enclustra Mercury KX1 FPGA Module USB 3.0 µC Kintex 7 FPGA MGTs DDR3 SDRAM Enclustra Mercury KX1 FPGA Module As a commercial board we are using Enclustra Mercury KX1 FPGA Module. Here you can see the main characteristics of the board such as USB 3.0 connectivity, Kintex-7 FPGA with multi-gigabit transceivers and SDRAM. Viacheslav Filimonov | The USBpix3 Readout System

7 Apr '14 Migrating from FX2 to FX3 Architectural Differences Here you can see architectural differences between FX2 device, that is used in a current MultiIO, and FX3 device, that is used in SuperIO. FX3 has many advantages, but the most important in our application are the following (CLICK): 100 MHz, 32 bit GPIF II interface in comparison with 48 MHz 16 bit GPIF interface of FX2 device and USB 3.0 functionality in comparison with USB 2.0 functionality of FX2 device. Viacheslav Filimonov | The USBpix3 Readout System

7 Apr '14 System (SuperIO) Firmware, software and hardware development Xilinx KX7 FPGA BRAM REGS + Quad module support (Bonn / Göttingen) USR PC (Host) FX3_IF DDR3 USB µC - STcontrol (Göttingen) - pyBAR (Bonn) UserApp Carrier board EEPROM USBLib Here you can see a block diagram of the developed firmware, software and hardware. In order to implement USB3.0 functionality in the new MultiIO, FX3 device was used. FX3 is a USB 3.0 microcontroller, that includes ARM CPU. One of the tasks was to develop a FW for it. It was necessary to implement USB3.0 interface in order to have a connection to PC. DMA handling had to be implemented as well to maximise the transfer speed between host and FPGA. LPPs had to be configured. GPIF interface had to be configured as well. GPIF interface is a General Programmable Interface that can be configured by user by the means of state machine. It is used in our application to control FPGA. Now FX3 microcontroller connects Host and FPGA via USB 3.0 and GPIF interfaces. Implemented I2C and SPI functionality provides access to EEPROM and SPI Flash via FX3 device. I2C and SPI transfers use DMA manual channels that suppose CPU intervention. GPIF transfers between Host and FPGA use DMA auto channels without CPU intervention for maximum speed. Developed FPGA firmware includes Block RAM, Registers, FX3_interface, DDR3 and user modules. FX3_interface module connects FPGA to USB mC and DDR3 module connects FPGA to DDR3 SDRAM. Therefore user has a possibility to access Block RAM, Registers or DDR3 SDRAM. Quad module support is available as well. Host software includes User application and a corresponding USB driver and library. Developed system will be downward compatible to STcontrol. Alternative application pyBAR can also be used with the system. (CLICK) FX3 device and KX7 FPGA are located on a commercial board. That is Enclustra Mercury KX1 FPGA Module, mentioned before. (CLICK) Therefore it was necessary to design a carrier PCB. Commercial board is connected with carrier PCB via two high speed board to board connectors. Carrier board is downward compatible to existing adapter cards. It is designed for high speed requirements. And provides functionality that is necessary for FE chip characterisation. DDR3 SDRAM SPI Flash USBDrv µC – FW ARM CPU USB3.0 DMA handling LPP handling GPIF config PCB design Downward compatibility High speed Functionality Commercial board Viacheslav Filimonov | The USBpix3 Readout System

7 Apr '14 Firmware development Speed test 32 bit databus; Burst length = 16; Buffer size = 32 kB; Buffer count = 2; Maximum block size = 4 Mbyte A speed test was performed for the FX3 device. 32 bit databus was used, Maximum block size to transfer was 4 Mbytes. Here are other parameters for DMA channels. Data transfer was realized between host and Block RAM of FPGA by the means of FX3. DMA auto channels were used for reading and writing in order to maximize the transfer speed. This is the block size of transfer and this is transfer rate for writing and reading. (Burst length = 16; Buffer size = 32 kB; Buffer count = 2 for both DMA channels). Maximum achieved reading speed was about 280 Mbyte/sec and writing speed was about 75 Mbyte/sec. And this result is very similar to the one I got while making tests with Streamer example from Cypress, that is intended to demonstrate the maximum speed. Reading speed ≈ 280 Mbyte/sec (2.24 Gbit/sec) Writing speed ≈ 75 Mbyte/sec (0.6 Gbit/sec) Viacheslav Filimonov | The USBpix3 Readout System

7 Apr '14 Firmware development Data integrity test 32 bit databus; Burst length = 16; Buffer size = 32 kB; Buffer count = 1 Data integrity tests were also made. All data integrity errors were corrected. Here you can see one of the results of the data integrity tests. Achieved speed ≈ 280 Mbyte/sec (Reading) Achieved speed ≈ 75 Mbyte/sec (Writing) Viacheslav Filimonov | The USBpix3 Readout System

7 Apr '14 Carrier Board SuperIO Buttons and LEDs User I/Os KEL Connector SMA connectors for external clock and MGTs Ethernet and LEMO connectors for trigger logic Enclustra KX1 FPGA Module JTAG Other components Clock Oscillator MHz Current Sense EEPROM PMOD Connector SuperIO consists of Enclustra KX1 FPGA Module and a carrier board. Developed carrier board includes such components as USB-B 3.0 Connector, JTAG, Gigabit Ethernet Connector, SMA connectors for external clock and MGTs, Ethernet and LEMO connectors for trigger logic. Buttons, LEDs and user I/Os are available as well. USB interface and KEL Connector makes it downward compatible to existing USBPix adapter cards and software. Power can be provided via external power supply or via USB. You can also find here Clock Oscillator, Current Sense, EEPROM and PMOD Connector. USB-B 3.0 Connector Gigabit Ethernet Connector Power Supply Viacheslav Filimonov | The USBpix3 Readout System

7 Apr '14 Conclusion Firmware development (still ongoing optimization) FPGA USB µC (FX3) USB library, driver (host software)  done Downward compatible to STcontrol (Göttingen) Alternative application – pyBAR (Bonn)  J. Janssen Carrier PCB development  done Testing Speed tests  2.24 Gbit/sec (Reading); 0.62 Gbit/sec (Writing) Data integrity test  Ok! Next steps Further FW optimization/debugging Implementation of Quad FE-I4 module R/O system (USBpix3) In conclusion I have to say that during the system development, FPGA and FX3 FW were developed. Currently optimization is ongoing. USB library and driver were developed for host software. Developed system will be downward compatible to STcontrol. Alternative application pyBAR can also be used with the system. Carrier PCB was developed as well. Speed and data integrity tests were made. Next steps include further FW optimization and debugging and Implementation of Quad FE-I4 module r/o system with USBpix3. Viacheslav Filimonov | The USBpix3 Readout System

7 Apr '14 Contact Information Viacheslav Filimonov Viacheslav Filimonov | The USBpix3 Readout System

7 Apr '14 BACKUP Viacheslav Filimonov | The USBpix3 Readout System

7 Apr '14 Research project overview Upgrade Plans for USBpix Commercial board (Linera FMU3-S6 Series FPGA Module) Custom made carrier PCB 65mm x 50mm board size USB3 Connectivity, including software drivers and APIs Xilinx Spartan6 LX45 application FPGA (Available also with LX150) 1Gbit DDR3 SDRAM (Optional 2 or 4 Gbit) MicroSD card slot, accessible from FPGA Very easy to integrate: Single 5V supply Programmable via USB3.0 port, JTAG or the on-board flash 2 100-pin high speed board-to-board connectors to mount on a host-board 150 user I/O signals. 72 differential pairs 8 User LEDs on-board Pin-compatible with FM-S651 series On-board, programmable clock generator with 4 output clocks, with available SSC FMU3-S6 series FPGA module One of the possible upgrade options is to use a commercial board with a custom made carrier PCB. Currently we are using a board from LINERA company that holds both FX3 and FPGA for firmware development. Here you can see the main characteristics of the board such as USB 3.0 connectivity, Spartan6 FPGA and 1Gbit SDRAM. Viacheslav Filimonov | The USBpix3 Readout System

7 Apr '14 Research project overview Upgrade Plans for USBpix Commercial board (Enclustra Mercury KX1 FPGA Module) Name FPGA Power supply On-board memory Expansion connector On-board clock synthesizer Oscillator Ethernet Other features USB 3.0 Price Enclustra (Mercury KX1) Xilinx Kintex-7 in the 676-pin FBG or high-performance FFG package 5-15V (Expansion connector) Up to MB DDR3 SDRAM (32-bit, 8-bit), Up to 64 MB Quad SPI Flash 2 x 168-pin Hirose FX10 (158 FPGA I/Os, single-ended or differential) No 200 MHz Dual Gigabit Ethernet Quad Gbps MGTs for PCIe 2.0 x4, 4 LEDs, RTC, Rechargeable Battery Yes €698 – 1450 Here you can see the main characteristics of the board such as USB 3.0 connectivity, Kintex-7 FPGA, multi-gigabit transceivers and SDRAM. Viacheslav Filimonov | The USBpix3 Readout System

7 Apr '14 Research project overview FX3 Firmware FX3 DVK Board USB 3.0 interface Firmware development FX3 device should be compatible with the software for the 8051 based USB 2.0 microcontroller FX3 device Cypress FX3 development board that includes USB 3.0 interface as well as a number of other interfaces was used for the firmware development for the FX3 device. FX3 device firmware should be compatible with the software for the 8051 based USB 2.0 microcontroller, that is currently used in the MultiIO board. Viacheslav Filimonov | The USBpix3 Readout System

7 Apr '14 Firmware development Here you can see the FX3 DVK Board Block Diagram. This board is used for the firmware development for the FX3 device. Firmware development for FX3 includes implementing (CLICK) USB, I2C, SPI and GPIF functionality. FX3 DVK Board Block Diagram Viacheslav Filimonov | The USBpix3 Readout System

7 Apr '14 Firmware development USB 3.0 Interface 4 endpoints for different transfer types were configured USB enumeration descriptors were configured DMA Manual channels were created between USB endpoints and CPU sockets FX3 is correctly recognized as SiUSB device on Windows 32 and 64-bit During the implementation of USB interface 4 endpoints for different transfer types were configured as well as USB enumeration descriptors. DMA Manual channels were created between USB endpoints and CPU sockets in order to send data to the host and receive data from it. FX3 device now is correctly recognized as SiUSB device on Windows 32 and 64-bit systems. (Ep 2 out, EP 6 in – Block transfers EP1 in/out – control transfers, slow peripherals) USB Device Manager interface Viacheslav Filimonov | The USBpix3 Readout System

7 Apr '14 Firmware development Low performance peripherals (LPP) I2C EEPROM Configuration of the interface parameters (100 KHz bit rate, register transfer mode, no bus timeout, no DMA timeout) I2C transfer (preamble: the slave address, the direction of the transfer, the address inside the slave; wait for ACK) SPI SPI Flash Configuration of the interface parameters (8 MHz SPI clock, 8 bits word length, MSB first data shift mode, idles high clock polarity (CPOL = 1), clock phase (slave samples at active-idle edge (CPHA = 1)), active low polarity of SSN line, slave select using FW) SPI transfer (location: command, page address; set SSN line, erase sector, wait for status) After implementing I2C and SPI functionality it’s possible to write and read data from EEPROM and SPI Flash using the software for the FX2 device. For I2C interface it was necessary to configure the interface parameters such as bit rate, transfer mode and timeouts as well as to realize the data transfer that is to configure the preamble and other interface specific features. For SPI interface it was necessary to configure interface parameters such as SPI clock, word length, data shift mode, clock polarity, clock phase, SSN line’s parameters as well as to realize the data transfer that is to configure the location and other interface specific features. Viacheslav Filimonov | The USBpix3 Readout System

7 Apr '14 Firmware development FX3 – FPGA connectivity GPIF II (General Programmable Interface) Functions as master or slave Provides 256 firmware programmable states Supports 8 bit, 16 bit, and 32 bit parallel data bus Enables interface frequencies up to 100 MHz Supports 14 configurable control pins when 32 bit data bus is used. All control pins can be either input/output or bidirectional Supports 16 configurable control pins when 16 or 8 data bus is used. All control pins can be either input/output or bidirectional FX3 - FPGA connectivity is realized with the GPIF interface. Here you can see the main characteristics of GPIF interface. It can function as master or slave; it provides 256 firmware programmable states; supports 8 bit, 16 bit, and 32 bit parallel data bus and enables interface frequencies up to 100 MHz. Viacheslav Filimonov | The USBpix3 Readout System

7 Apr '14 Firmware development GPIF II Designer Define the interface in the form of a state machine diagram The electrical interfacing details should be defined using the Interface definition tab before entering the state machine using the state machine canvas tab To configure the GPIF port of FX3 device to connect to the FPGA a software tool called GPIF designer is used. It allows to define the interface in the form of a state machine diagram as well as to define the electrical interfacing details. Viacheslav Filimonov | The USBpix3 Readout System

7 Apr '14 Firmware development GPIF II Designer In our case electrical interfacing details look like this: we are using I2C, SPI is implemented in the firmware but it’s not possible to use it with 32 bit databus. FX3 is a master in this case, communication type is synchronous, internal clock is used with positive clock edge, data bus width is 32 bits. Some control signals are also used. All signals are currently set to active high. Viacheslav Filimonov | The USBpix3 Readout System

7 Apr '14 Firmware development GPIF II Designer The interface itself is defined in the form of a state machine diagram. Here you can see a state machine that consists of 2 parts: for writing and for reading. First of all after application is started and GPIF interface is initialized the state machine goes to RESET state where it drives Reset GPIO to reset the FPGA. Then it goes to LD_COUNTERS state where counters are initialized. After this it loops between IDLE_READ and IDLE_WRITE states. Then depending on the type of the request from the host it switches to the reading part of state machine or to the writing part of the state machine. The first state in writing state machine is IDLE_WR. It will go to the Start Of Frame state if the data in the corresponding DMA socket is available. If it is it goes to the Start Of Frame state and drives corresponding gpios that signal FPGA about the start of frame. FPGA answers with acknowledge. The next state is for driving data to the databus. Here the data counter is used based on the length of the data that should be written to FPGA. WAIT state is necessary if in some moment during the transition there is no valid data in the socket. After data is driven to the databus the data counter hit condition becomes true and state machine goes to the End Of Frame state and waits for the acknowledge from the FPGA. Here another counter is used to implement a time-out. I have to mention that all data transfers with GPIF interface are done with the help of DMA Factory without CPU intervention. Viacheslav Filimonov | The USBpix3 Readout System

7 Apr '14 Firmware development IDLE SOF WR_DATA EOF IDLE Here is what we had on the scope during writing to the FPGA when 16 bit databus was used. (CLICK) All the states are passed according to the state machine. IDLE, SOF, WR_DATA, EOF and again IDLE. Viacheslav Filimonov | The USBpix3 Readout System

7 Apr '14 Firmware development FX3 device: Can be programmed with software for the FX3 development kit (USB 3.0) FPGA: Can be programmed with JTAG interface (self-made connector + USB-JTAG Programming Cable) FX3 device on this board can be programmed with the software provided for FX3 development kit through USB. FPGA can be programmed with JTAG interface through the self-made connector and USB-JTAG Programming Cable. It’s enough to start testing. FMU3-S6 connected to the power supply, to the host through USB 3.0 interface and to the USB-JTAG Programming cable through the self-made connector. Viacheslav Filimonov | The USBpix3 Readout System

7 Apr '14 Firmware development Response from the FPGA (Timing) In order to program a correct response from the FPGA it is necessary to take into account such GPIF timing parameters as data and control signals to clock setup time, to clock hold time, propagation delays and some others. Viacheslav Filimonov | The USBpix3 Readout System

7 Apr '14 Firmware development GPIF II Designer (Timing simulation) Some of the timing parameters are also reflected in the GPIF designer timing simulation. This is a simulation of a writing state machine. Here it’s possible to see not only data and control signals but also DMA and counter flags. Viacheslav Filimonov | The USBpix3 Readout System

7 Apr '14 Firmware development Response from the FPGA to the reading access (FX3 delay) Response from the FPGA to the writing access (FX3 delay) Writing and reading responses have been written for FPGA taking into account GPIF timing parameters. So that FPGA can distinguish the start of frame and give certain response for FX3. Here are ISim simulations for reading and writing responses. Viacheslav Filimonov | The USBpix3 Readout System

7 Apr '14 Firmware development Response from the FPGA to the reading access (FX3 + FPGA delay) Response from the FPGA to the writing access (FX3 + FPGA delay) And here you can see ISim simulations where FPGA delays have also been taken into account. After the delays’ analysis was finished the firmware for the FX3 and FPGA was adapted to delays. Viacheslav Filimonov | The USBpix3 Readout System

7 Apr '14 Firmware development ChipScope waveform (Writing to the FPGA) ChipScope core was inserted in the FPGA firmware in order to monitor real data and control signals from FX3 and FPGA. Here you can see ChipScope waveform that was captured during writing access to the FPGA. In order to have a correct waveform it was necessary to modify FX3 and FPGA firmware. Viacheslav Filimonov | The USBpix3 Readout System

7 Apr '14 Firmware development IO Test Single word access to the FPGA Block RAM Now it’s possible to write and to read single words from the FPGA BRAM with the help of USB Device Manager. Achieved speed ≈ 280 Mbyte/sec (Reading) Achieved speed ≈ 75 Mbyte/sec (Writing) Viacheslav Filimonov | The USBpix3 Readout System

7 Apr '14 Firmware development Speed test 16 bit databus; Burst length = 16; Buffer size = 16 kB; Buffer count = 1 (Writing DMA Channel), = 2 (Reading DMA Channel) 16 bit databus; Burst length = 16; Buffer size = 16 kB; Buffer count = 2 A number of speed tests were made in order to get the maximum transfer rate during writing and reading. Here you can see speed tests with 16 bit databus. Burst length = 16; Buffer size = 16 kB; Buffer count = 1 (for Writing DMA Channel), 2 (for Reading DMA Channel) in the first test, and 2 for both DMA channels in the second test. Maximum achieved reading speed was about 170 Mbyte/sec and writing speed was about 60 Mbyte/sec. Achieved speed ≈ 170 Mbyte/sec (Reading) Achieved speed ≈ 60 Mbyte/sec (Writing) Viacheslav Filimonov | The USBpix3 Readout System

7 Apr '14 Firmware development Speed test 32 bit databus; Burst length = 16; Buffer size = 16 kB; Buffer count = 2 32 bit databus; Burst length = 16; Buffer size = 32 kB; Buffer count = 2 And here you can see speed tests with 32 bit databus. Burst length = 16; Buffer size = 16 kB in the first test and = 32 kB in the second test; Buffer count = 2 for both DMA channels. Maximum achieved reading speed was about 240 Mbyte/sec and writing speed was about 60 Mbyte/sec. Achieved speed ≈ 240 Mbyte/sec (Reading) Achieved speed ≈ 60 Mbyte/sec (Writing) Viacheslav Filimonov | The USBpix3 Readout System

7 Apr '14 Firmware development Speed test (Streamer application) 32 bit databus; In endpoint; Burst length = 16; Buffer size = 32 kB; Buffer count = 2 32 bit databus; Out endpoint; Burst length = 16; Buffer size = 32 kB; Buffer count = 2 Here you can see the best results I got with the Streamer application. Data transfer was realized between host and FX3, independently from FPGA. Maximum achieved reading speed was about 286 Mbyte/sec and writing speed was about 78 Mbyte/sec. Achieved speed ≈ 286 Mbyte/sec Achieved speed ≈ 78 Mbyte/sec Viacheslav Filimonov | The USBpix3 Readout System

Backup EZ USB FX3 System Diagram SPI Flash 4 Mbit EEPROM 64kB
7 Apr '14 Backup EZ USB FX3 System Diagram SPI Flash 4 Mbit EEPROM 64kB Viacheslav Filimonov | The USBpix3 Readout System

Backup EZ USB FX3 System Diagram 7 Apr '14
Viacheslav Filimonov | The USBpix3 Readout System

7 Apr '14 Backup (Currently 8 MHz) Viacheslav Filimonov | The USBpix3 Readout System

7 Apr '14 Backup Viacheslav Filimonov | The USBpix3 Readout System

7 Apr '14 Backup Programming View of FX3 Viacheslav Filimonov | The USBpix3 Readout System

7 Apr '14 Backup DMA Mechanism System Memory Viacheslav Filimonov | The USBpix3 Readout System

7 Apr '14 Backup DMA Components Viacheslav Filimonov | The USBpix3 Readout System

7 Apr '14 Backup USB Comparison Viacheslav Filimonov | The USBpix3 Readout System

7 Apr '14 Backup Changes in USB 3.0 SuperSpeed — New higher signaling rate of 5Gbps (625MB/sec) Dual-bus architecture — Low-Speed, Full-Speed, and High-Speed bus plus SuperSpeed bus Asynchronous instead of polled traffic flow Dual-simplex simultaneous bi-directional data flow for SuperSpeed instead of half-duplex unidirectional data flow Support for streaming Fast Sync-N-Go technology Support for higher power Better power management Viacheslav Filimonov | The USBpix3 Readout System

7 Apr '14 Backup USB 3.0 Pin Description Electrical Interface USB 3.0’s pinout is different from that of USB 2.0. Besides the VBUS, D-, D+, and GND pins required for 2.0, 3.0 has five additional pins – two differential pairs plus one ground (GND_DRAIN). The two differential pairs are for SuperSpeed data transfer, supporting dual simplex SuperSpeed signaling. The added GND_DRAIN pin is for drain wire termination, managing signal integrity, and EMI performance. For high throughput and biwire transfer, USB 3.0 defines nine pins to enhance this feature. These pins contain four pins for USB 2.0 and five additional pins for 3.0. Table 1 shows the description of these nine pins. Viacheslav Filimonov | The USBpix3 Readout System

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