1. DISEÑO DE CIRCUITOS LOGICOS SECUENCIALES
En el desarrollo de los Sistemas Digitales es fundamental el almacenamiento de información, característica permitida por los Circuitos Lógicos Secuenciales.
Los circuitos lógicos secuenciales se asocian al estudio de dispositivos de almacenamiento en general y en donde una de sus características principales es que sus salidas dependen de las entradas actuales, de entradas en tiempos anteriores y de una señal externa de reloj.
© ILCEO: ING. MIGUEL ANGEL PEREZ SOLANO

2. STORAGE ELEMENTS
• Previously, we have considered combinational circuits where the output values depend only on the values of signals applied to the inputs
• Another class of logic circuits have the property that the outputs depend not only on the current inputs, but also on the past behavior of the circuit.
• Such circuits include storage elements that store the values of logic signals.
SEQUENTIAL CIRCUITS
• Contents of the storage elements represent the state of the circuit
• Input value changes may leave the circuit in the same state or cause it to change to a new state
• Over time, the circuit changes through a sequence of states as a result of changes in the inputs
• Circuits that exhibit this behavior are referred to as sequential circuits

3. Sequential circuits usually contain combinational
subcircuits and feedback paths.

4. • A similar circuit, constructed with NOR gates can also
BASIC SR LATCH
• A similar circuit, constructed with NOR gates can also
be constructed
• Inputs, Set and Reset, provide the means to
changing the state, Q, of the circuit
• This circuit is referred to as a basic latch
• When R=S=0 the circuit remains in its current state (either
Qa=1 and Qb=0 or Qa=0 and Qb=1).
• When S=1 and R=0, the latch is set into a state where Qa=1 and Qb=0
• When S=0 and R=1, the latch is reset into a state where Qa=0 and Qb=1
• Where S=1 and R=1, Qa=Qb=0 (there are actually problems with this state as we will see)

6. Basic SR latch timing diagram

7. GATED SR LATCH
• The basic SR latch changes its state whenever its inputs change
• It may be desirable to add an enable signal to the basic SR latch that allows us to control when the circuit can change states
• Such a circuit is referred to as a gated SR
latch

9. GATED SR LATCH TIMING DIAGRAM
GATED SR LATCH WITH NAND GATES

10. GATED D LATCH
• Another useful latch has a single data input, D, and it stores the value of this input under the control of a clock signal
• This is referred to as a gated D latch
– Useful in circuits where we want to store some value
– The output of an adder/subtractor circuit would be one example

11. GATED D LATCH

12. LEVEL VERSUS EDGE SENSITIVITY
• Since the output of the D latch is controlled by the level (0 or 1) of the clock input, the latch is said to be level sensitive
– All of the latches we have seen have been level sensitive
• It is possible to design a storage element for which the output only changes a the point in time when the clock changes from one value
to another
• Such circuits are said to be edge triggered

13. EFFECTS OF PROPAGATION DELAYS
• Previously we have ignored the effects of propagation delay. In practical circuits, it is essential to account for these delays
• For the gated D latch (and others as well), it is important that the value of D not change at the time the clock (clk) goes from 1 to 0
– The designer must make sure the signal is stable when the critical change in the clock takes place
• The minimum time the D signal must remain stable prior to the negative edge (1->0) of the clock signal is called the setup time (tsu)
• The minimum time the D signal must remain stable after the negative edge of clock is the hold time (th)
– Typical CMOS values are: tsu=3ns and th=2ns

14. SETUP AND HOLD TIMES

15. FLIP-FLOPS
• The gated latch circuits presented are level sensitive and can change states more than once during the ‘active’ period of the clock signal
• Circuits (storage elements) that can change their state no more than once during a clock period are also useful
• Two types of circuits with such behavior
– Master-slave flip-flip
– Edge-triggered flip-flop

16. MASTER-SLAVE D FLIP-FLOP
• Consists of 2 gated D latches:
– The first, master, changes its state while clock=1
– The second, slave, changes its state while clock=0

17. MASTER-SLAVE D FLIP-FLOP
• When clock=1, the master tracks the values of the D input signal and the slave does not change
– Thus Qm follows any changes in D and Qs remains constant
• When the clock signal changes to 0, the master stage stops following the changes in the D input signal
• At the same time, the slave stage responds to the value of Qm and changes states accordingly
• Since Qm does not change when clock=0, the slave stage undergoes at most one change of state during a clock cycle
• From an output point of view, the circuit changes Qs (its output) at the negative edge of the clock signal

18. MASTER-SLAVE D FLIP-FLOP

19. EDGE-TRIGGERED FLIP-FLOP
• A circuit, similar in functionality to the master-slave D flip-flop, can be constructed with 6 NAND gates

20. EDGE-TRIGGERED FLIP-FLOP
• The previous circuit responds on the positive edge of the clock signal
• A negative-edge triggered D flip-flop can be constructed by replacing the NAND with NOR gates

21. COMPARING D STORAGE ELEMENTS

22. CLEAR AND PRESET INPUTS
• It may be desirable to specifically set (Q=1) or clear (Q=0) a flip-flop
• Practical flip-flops often have preset and clear inputs
– Generally, these inputs are asynchronous (they do not depend on the clock signal)

23. T FLIP-FLOP
• Another flip-flop type, the T flip-flop, can be derived from the basic D flip-flop presented
• Feedback connections make the input signal D equal to the value of Q or Q’ under control of a signal labeled T

24. T FLIP-FLOP
• The name T derives from the behavior of the circuit, which ‘toggles’ its state when T=1
– This feature makes the T flip-flop a useful element when constructing counter circuits

25. JK FLIP-FLOP
• The JK flip-flop can also be derived from the basic D flip-flop such that
D=JQ’+K’Q
• The JK flip-flop combines aspects of the SR and the T flip-flop
– It behaves as the SR flip-flop (where J=S andK=R) for all values except J=K=1
– For J=K=1, it toggles like the T flip-flop

26. JK flip-flop timing diagram

27. • A flip-flop stores one bit of information.
REGISTERS
• A flip-flop stores one bit of information.
• When a set of n flip-flops is used to store n bits of data, we refer to these flip-flops as a register
– Common register usages include
• Holding a data value output from an arithmetic circuit
• Holding a count value in a counter circuit
• A common clock signal is typically used for each flip-flop in a register

28. SHIFT REGISTER
• A register that provides the ability to shift its contents by a single bit
– May be to the right or left (or possibly both)

29. SHIFT RIGHT REGISTER
• Data is shifted to the right in a serial fashion using the In input
• Positive edge triggered
– Contents of each flip-flop are transferred to the next flip-flop at each positive edge of the clock
• Level sensitive devices would not be appropriate for this
circuit

30. PARALLEL-ACCESS SHIFT REGISTER
• Data transfer in computer systems is a common function
– If the transfer is n-bits at a time, the transfer is said to be in parallel
– If the transfer is 1-bit at a time, the transfer is said to be serial
• To transfer data serially, data is loaded into a register in parallel (in one clock cycle) and then shifted out one bit at a time
– Parallel-to-serial data conversion
• If bits are received serially, after n clock cycles the contents of a register can be accessed in parallel as an n-bit item
– Serial-to-parallel conversion

31. PARALLEL-ACCESS SHIFT REGISTER

32. COUNTERS
• Special purpose arithmetic circuits used for the purpose of counting
– Design circuits that can increment or decrement a count by 1
• Counter circuits server many purposes
– Count occurrences of certain events
– Generate timing intervals for controlling various tasks in a digital system
– Track elapsed time between events
• Often (but not always) built with T flip-flops because the toggle feature is naturally suited for implementing the counting operation

33. UP-COUNTER WITH T FLIP-FLOPS

34. DOWN COUNTER WITH T FLIP-FLOPS

35. ASYNCHRONOUS COUNTERS
• The previous counters are examples of asynchronous counters. Also called ripple counters.
– Input clock is only connected to one flip-flop
– Clocks for other flip-flops are (or are derived from) the outputs of the previous flip-flops
• This form of counter is slow because the cascaded clocking scheme
– The clock source ripples from stage-to-stage
– The ripple effect is similar to that of a ripple carry adder circuit

36. SYNCHRONOUS COUNTERS
• Synchronous counters are built by clocking all the flip-flops at the same time (with a single clocking source)
– Faster response than
asynchronous counters
• Synchronous counters with T flip-flops
– Least significant bit, Q0, changes every clock cycle
– Bit one, Q1, only changes when Q0=1
– Bit two, Q2, only changes when Q0=Q1=1

37. T FLIP-FLOP SYNCHRONOUS COUNTER

38. ENABLE AND CLEAR CAPABILITY
• It may be desirable to disable counting or clear the counter
– Include an enable control signal
– Use a flip-flop with asynchronous clear capability

39. D FLIP-FLOP SYNCHRONOUS COUNTER
• A 4-bit up counter counts in the sequence 0,1,2,…,15,0,1…
• The count is given by the flip-flop outputs Q3Q2Q1Q0
• The D inputs are given by:
D0=Q0⊕Enable
D1=Q1⊕Q0⋅Enable
D2= Q2⊕Q1⋅Q0⋅Enable
D3= Q3⊕Q2⋅Q1⋅Q0⋅Enable

40. FOUR-BIT COUNTER (D FLIP-FLOPS)

41. COUNTERS WITH PARALLEL LOAD
• It is common for counters to begin a count with a zero value
– An asynchronous clear input can be used for his purpose
• It may be desirable for a counter to begin with a non-zero value
• Adding circuitry to provide parallel load capability is necessary
• A control input, load, is used to select a mode of operation
– Load=0, circuit counts
– Load=1, parallel load a new value into the counter

42. PARALLEL LOAD COUNTER

43. SYNCHRONOUS SEQUENTIAL CIRCUITS
• Circuits where a clock signal is used to control operation are called synchronous sequential circuits
– The term active clock edge refers to the clock edge that causes a change in state (positive or negative)
• Realized using combinational logic and one or more flip-flops
• Two models for synchronous sequential circuits
– Moore model: circuit outputs depend only on the present state of the circuit
– Mealy model: circuit outputs depend on the present state of the circuit and the primary inputs
• Sequential circuits are also called finite state
machines (FSM)

44. MOORE VERSUS MEALY MACHINES

45. BASIC DESIGN STEPS
• We will introduce techniques for sequential circuit design via a simple example
• Design a circuit that meets the following specifications:
– The circuit has one input, w, and one output, z
– All changes in the circuit occur on the positive edge of the clock signal
– Output z=1 if the input w was 1 during the two immediately preceding clock cycles
• From this specification it is obvious that z cannot depend solely of the value of w

46. SEQUENCES OF SIGNALS STATE DIAGRAM
• The example input and output sequence below aides in the description of the circuit
STATE DIAGRAM
• The first step in designing an FSM is determining how many states are needed and which transitions are possible from onestate to another
– No preset procedure for this
– The designer must think about what the circuit is to accomplish
• A good beginning is to define a reset state that the circuit should enter when power is applied or when a reset signal is received

47. STATE DIAGRAM • For our example, assume the starting state is called A
• As long as w=0, the circuit should do nothing and z=0
• When w=1, the circuit should ‘remember’ this
by transitioning to a new state (B)
• This transition should occur at the next
positive edge of the clock signal

48. COMPLETE STATE DIAGRAM
• When in state B and w=1, the circuit should remember’ this by transitioning to a new‘state (C)
COMPLETE STATE DIAGRAM
Moore model state diagram

49. STATE TABLE
• A state diagram describes circuit functionality, but does not describe circuit implementation
• Translation to a tabular form is necessary
• The state table should contain
– All transitions from each present state to each next state for all valuations of the input signals
– The output, z, is specified with respect to the present state

50. STATE ASSIGNMENT
• The states are defined in terms of variables (A, B, and C)
• Each state is represented by a particular valuation of state variables
• Each state variable is implemented with a flip-flop
• Since three states have to be realized, it is sufficient to use two state variables
– Use y2y1 for the present state (present state variables)
– Use Y2Y1 for the next state (next state variables)

51. STATE-ASSIGNED TABLE
Note the addition of the y2y1=11 state. Although it is not used, it is needed for completeness.

52. NEXT-STATE AND OUTPUT MAPS
• K-maps are constructed from the state table for:
– Circuit outputs (z in this case)
– Inputs for the flip-flops (next-state K-maps)
• Constructing the next-state maps depends on the type of flip-flop (D, T, JK) used for theimplementation
– D is the most straightforward: next-state mapsare constructed directly from the state table since
• Q(t+1)=Q+=D
– T and JK implementations will be covered later

53. STATE TABLE AND NEXT-STATE MAPS

54. STATE TABLE AND OUTPUT MAP

55. CIRCUIT DIAGRAM

56. TIMING DIAGRAM

57. COUNTER DESIGN EXAMPLE
• Design a 2-bit counter that counts
– in the sequence 0,1,2,3,0,… if a given control signal U=1, or
– in the sequence 0,3,2,1,0,… if a given control signal U=0
• This represents a 2-bit binary up/down counter
– An input U to control to count direction
– A RESET input to reset the counter to the value zero
– Two outputs (Z1 Z0) representing the output (0-3)
– Counter counts on positive edge transitions of a common clock signal
• Design this counter as a synchronous sequential machine using
– D-type, T-type, JK-type flip-flops

58. COUNTER STATE DIAGRAM
COUNTER STATE TABLE

59. STATE-ASSIGNED STATE TABLE
• Choosing a state assignment of A=00, B=01, C=10 and D=11 makes sense here because the outputs Z1Z0 become the outputs from the flip-flops directly

60. D-TYPE FLIP-FLOP IMPLEMENTATION
• When D flip-flops are used to implement an FSM, the next-state entries in the stateassigned state table correspond directly tothe signals that must be applied to the D inputs
• Thus, K-maps for the D inputs can be derived directly from the state-assigned state table
• This will not be the case for the other types of flip-flops (T, JK)

61. STATE TABLE AND NEXT-STATE MAPS

62. CIRCUIT DIAGRAM (D FLIP-FLOP)

63. DESIGN USING OTHER FLIP-FLOP TYPES
• For the T- or JK-type flip-flops, we must derive the desired inputs to the flip-flops
• Begin by constructing a transition table for the flip-flop type you wish to use
– This table simply lists required inputs for a given change of state
• The transition table is used with the stateassigned state table to construct an
excitation table
– The excitation table lists the required flip-flop
inputs that must be ‘excited’ to cause a transition
to the next state

64. TRANSITION TABLES

65. T-TYPE FLIP-FLOP IMPLEMENTATION

66. EXCITATION TABLE AND K-MAPS

67. CIRCUIT DIAGRAM (T FLIP-FLOP)

68. JK-TYPE FLIP-FLOP IMPLEMENTATION
• Use entries from the transition table to derive the flip-flop inputs based on the state-assigned state table
– This must be done for each input (J and K) on each flip-flop

69. JK-TYPE FLIP-FLOP IMPLEMENTATION

70. EXCITATION TABLE AND K-MAPS

71. EXCITATION TABLE AND K-MAPS

72. CIRCUIT DIAGRAM (JK FLIP-FLOP)

73. STATE ASSIGNMENT GUIDELINES
1. States that have the same next state for a given input should be
given adjacent assignments
2. States that are the next state of the same state should be given adjacent assignments.
• Keep the following in mind:
1. Assign the starting state to the ‘0’ cell on the map (i.e. the starting state has all flip-flop outputs=0)
2. Satisfy guideline 1 and multiple occurrences of guideline 2 first
3. If the guidelines require that 3 or 4 states be adjacent, place these states within a group of 4 adjacent squares on the map
4. Guideline 3 is less important than 1 or 2 unlessthe circuit is to have multiple outputs

74. EXAMPLE MOORE STATE DIAGRAM

75. EXAMPLE STATE ASSIGNMENT

76. MEALY STATE MODEL
• Mealy model: circuit outputs depend on the present state of the circuit and the primary inputs, giving additional flexibility in designing sequential circuits
• Greater flexibility often leads to simpler circuits

77. MEALY STATE DIAGRAM
• For the Mealy model, outputs are no longer associated with a particular state
– Outputs are associated with transitions between states
• Typical Mealy model state diagram
– Detects w=11 sequence

78. MEALY MODEL STATE TABLE
• The state table for a Mealy model FSM differs from the Moore model FSM only in how theoutputs are viewed

79. STATE-ASSIGNED STATE TABLE
Design example
• Construct a Mealy state diagram for a sequence detector that detects the input sequence w=101

80. NOTAS DEL CURSO