1. EGR 2131 Unit 9 Registers and Counters
Read Mano & Ciletti, Chapter 6.
Homework #9 and Lab #9 due in 1.5 weeks.
Quiz in 1.5 weeks.
-Do Quiz #8.
-Handouts: Unit 9 Practice Sheet.

2. Basic Shift Register Operations
A shift register is a digital circuit with two basic functions: data storage and data movement. Some basic data movements are illustrated here.
Data in
Data in
Data out
Data out
Data in
Data out
Serial in/shift right/serial out
Serial in/shift left/serial out
Parallel in/serial out
Data in
-Not very glamorous, but important.
-After this slide, quickly jump to UART slide below, and then come back here.
Data in
Data out
Data out
Serial in/parallel out
Parallel in/parallel out
Rotate right
Rotate left

3. Serial-in/Serial out Shift Register
Shift registers are available in IC form or can be constructed from discrete flip-flops, as shown here with a five-bit serial-in serial-out register.
Each clock pulse will move an input bit to the next flip-flop. For example, a 1 is shown as it moves across. 1 1 1 1 1 1
-Demo with Multisim file shiftReg.ms10.
CLK
CLK
CLK
CLK
CLK

4. A Basic Application
One application of shift registers is conversion of serial data to parallel form.
For example, assume the binary number 1011 is loaded sequentially, one bit at each clock pulse.
After 4 clock pulses, the data is available at the parallel output.
CLK
CLK
CLK
CLK

5. The 74164 is an 8-bit serial in/parallel out shift register.
The Shift Register
The is an 8-bit serial in/parallel out shift register.
MR is an input, so it really
belongs on the left side with
the other inputs instead of on
the bottom with the outputs.
As with counters, we usually show LSB on left and MSB on right. Data is shifted into Q0.
One of the two serial data inputs may be used as an active HIGH enable to gate the other input. If no enable is needed, the other serial input can be connected to VCC. The has an active LOW asynchronous clear (MR). Data is entered on the rising edge of the clock.

6. Waveforms for the 74164
Sample waveforms for the are shown. Notice that B acts as an active HIGH enable for the data on A. MR
DSa
Serial inputs
DSb
CLK Q0 Q1 Q2 Q3
-Do Practice Question 1.
Outputs Q4 Q5 Q6 Q7
Clear
Clear

7. The 74165 is an 8-bit parallel in/serial out shift register.
The Shift Register
The is an 8-bit parallel in/serial out shift register.
-This one’s harder to visualize because you can only see the bits when they pop out on the right-hand end (Q7). Before they get there, they march unseen through the register.
-LOAD is asynchronous.
Data is loaded asynchronously when PL is LOW. Data is shifted through the register synchronously when PL is HIGH and a rising clock edge occurs.

8. Universal Shift Register
A universal shift register has both serial and parallel input and output capability. The is an example of a 4-bit bidirectional universal shift register.
S1 S0 Mode
Hold
Shift right
Shift left
Parallel load (synchronous)
Sample waveforms on the following slide…

9. Universal Shift Register
-Do Practice Question 2.

10. Some Shift Register Chips
74164 (8-bit serial in/parallel out)
74165 (8-bit parallel in/serial out)
74194 (4-bit bidirectional universal)
74195 (4-bit parallel access)

11. Example Solution Shift Register Applications
Shift registers can be used to delay a digital signal by a predetermined amount.
An 8-bit serial in/serial out shift register has a 40 MHz clock. What is the total delay through the register?
Example
Solution
The delay for each clock is 1/40 MHz = 25 ns
-Do as Practice Question 3.
25 ns
The total delay is 8 x 25 ns = 200 ns
= 200 ns

12. Shift Register Applications
Data bus
A UART (Universal Asynchronous Receiver Transmitter) is a serial-to-parallel converter and a parallel to serial converter.
UARTs are commonly used in small systems where one device must communicate with another. Parallel data is converted to asynchronous serial form and transmitted. The serial data format is:
CLK
CLK
Serial data out
Serial data in
Start
Bit (0)
Stop Bits (1)

13. Cascading Shift Registers
Most shift register chips are 4-bit or 8-bit shift registers.
To get larger shift registers, you can cascade two or more chips together.
For a circuit in Lab #12 you’ll need to think about how to do this. 13

14. Shift Counters
Shift registers can form useful counters by recirculating a pattern of 0’s and 1’s. Two important shift counters are the ring shift counter and the Johnson shift counter.

15. Ring Shift Counter
The ring shift counter can be implemented with either D flip-flops or J-K flip-flops.
Here is a 4-bit ring shift counter constructed from a series of D flip-flops. Notice the feedback.
It can also be implemented with J-K flip flops.

16. Ring Shift Counter
Redrawing the ring shift counter (without the clock shown) shows why it is a “ring”.
In practical applications, the counter is preloaded with the desired pattern (usually a single 0 or 1).
It has n states, where n = number of flip-flops.

17. Ring Shift Counter
A common pattern for a ring shift counter is to load it with a single 1 or a single 0. The waveforms shown here are for an 8-bit ring shift counter with a single 1.
-Do Practice Question 4.
-Demo with Multisim file shiftCounter.ms10.

18. Johnson Shift Counter
The Johnson shift counter can be made with D flip-flops…
… or with J-K flip flops. Here Q3 and Q3 are fed back to the J and K inputs with a “twist”.

19. Johnson Shift Counter
Redrawing the same Johnson shift counter (without the clock shown) illustrates why it is sometimes called as a “twisted-ring” counter.
“twist”
-Demo by modifying Multisim to change from ring shift counter to Johnson shift counter.

20. Question Johnson Shift Counter
The Johnson shift counter is useful when you need a sequence that changes by only one bit at a time but it has a limited number of states (2n, where n = number of stages).
The first five counts for a 4-bit Johnson counter that is initially cleared are: CLK Q0 Q1 Q2 Q3 1 2 3 4 5 6 7
-Do Practice Question 5.
Question
What are the remaining 3 states?

21. Keyboard Encoder
The keyboard encoder is an example of where a ring counter is used in a small system to encode a key press.
Two shift registers are connected as an 8-bit ring counter preloaded with a single 0. As the 0 circulates in the ring counter, it “scans” the keyboard looking for any row that has a key closure. When one is found, a corresponding column line is connected to that row line. The combination of the unique column and row lines identifies the key. The schematic is shown on the following slide…

22. 8-bit ring counter (two cascaded 74195s)
74147s used as keyboard encoders (similar to example from Unit 8 slides)
© 2008 Pearson Education

23. Comparison of Counters & Shift Registers
4-bit Asynchronous Counter:
4-bit Synchronous Counter:
4-bit Shift Register:
-Do Practice Question 6.
-Actually more common to use D-flip-flops for a shift reg (as shown on Slide #4), rather than J-K. 23

24. Counting in Binary
As you know, the binary count sequence follows a familiar pattern of 0’s and 1’s as described in Section 2-2 of the text.
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
LSB changes on every number.
The next bit changes on every other number.
The next bit changes on every fourth number.

25. Counting in Binary
A counter can form the same pattern of 0’s and 1’s with logic levels. The first stage in the counter represents the least significant bit – notice that these waveforms follow the same pattern as counting in binary.
LSB
-How does a single JK flip-flop in toggle mode behave? It’s a MOD-2 counter (or divide-by 2 counter) that counts from 0 to 1 and then recycles.
-Basic idea for higher-MOD counters is to connect several flip-flops together in such a way that they count up from 0 to some terminal state, at which point they recycle back to 0.
-Two main ways to do this: asynchronous (ripple) counters and synchronous counters, both with many variations. Preview by drawing two-bit counters, and do Practice Questions 7, 8.
MSB

26. Synchronous versus Asynchronous
The synchronous/asynchronous distinction has different meanings:
As applied to inputs: A change on a synchronous input doesn’t affect the outputs until the next active clock edge, but a change on an asynchronous input affects the outputs immediately. 26

27. Synchronous versus Asynchronous
The synchronous/asynchronous distinction has different meanings:
As applied to counters: in a synchronous counter, the outputs can all change at the same instant; but in an asynchronous counter, there’s a brief delay between the changing of the outputs. 27

28. Three bit Asynchronous Counter
In an asynchronous counter, the clock is applied only to the first stage. Each subsequent stage gets its clock from the previous stage.
The asynchronous counter shown is a three-bit counter (also called MOD-8 counter or divide-by-8 counter). It uses J-K flip-flops in the toggle mode.
CLK K0 J0 Q0 C J1 J2 K1 K2 Q1 Q2
HIGH
Note these are positive-edge-triggered flip-flops, that’s why clocks are driven from Q’ output.
Waveforms are on the following slide…

29. Three bit Asynchronous Counter
Notice that the Q0 output is triggered on the rising edge of the clock signal. The following stage is triggered from Q0. The rising edge of Q0 is equivalent to the falling edge of Q0. The resulting sequence is that of a 3-bit binary up counter.
CLK Q0 Q1 Q2

30. Terminology: Modulus and Divide-By
CLK K0 J0 Q0 C J1 J2 K1 K2 Q1 Q2
HIGH
As noted on an earlier slide, the three-bit counter shown here is also called a MOD-8 counter or a divide-by-8 counter.
A counter’s modulus is the number of different values it can count through. The example shown has a modulus of 8. (The eight values are 000, 001, 010, 011, 100, 101, 110, 111.)
Also, the signal at Q2 will have a frequency equal to one-eighth of the incoming clock frequency. That’s why we can call it a divide-by-8 counter. 30

31. Propagation Delay
Asynchronous counters are sometimes called ripple counters, because the stages do not all change together. For certain applications requiring high clock rates, this is a major disadvantage.
Notice how delays are cumulative as each stage in a counter is clocked later than the previous stage.
CLK Q0 Q1 Q2
Q0 is delayed by 1 propagation delay, Q1 by 2 delays and Q2 by 3 delays.

32. The 74LS93 Asynchronous Counter
The 74LS93 has one independent toggle J-K flip-flop driven by CLK A and three toggle J-K flip-flops that form an asynchronous counter driven by CLK B.
The counter can be extended to form a 4-bit counter by connecting Q0 to the CLK B input. Two inputs are provided that clear the count.
CLK B J0 J1 J2 J3
CLK A C C C C
We’ve used this chip in Labs 1, 2, and 8. K0 K1 K2 K3
All J and K inputs are connected internally HIGH
RO (1)
RO (2) Q0 Q1 Q2 Q3

33. Some Asynchronous Counter ICs
7490 Four bit decade counter (MOD 10)
7492 Four bit divide-by-12 counter (MOD 12)
7493 Four bit binary counter (MOD 16)
Do Practice Questions 9, 10.

34. Asynchronous Decade Counter
This counter uses a NAND gate to recycle the count sequence to zero after the 1001 state, resulting in a MOD-10 counter (or decade counter). Other truncated sequences can be obtained using a similar technique.
CLR
CLK K0 J0 Q0 C J1 J2 K1 K2 Q1 Q2
HIGH J3 K3 Q3
-Variation on the basic counter, except extra gates force the count back to 0 before it gets all the way up to 15. This is called a truncated sequence.
Waveforms are on the following slide…

35. Asynchronous Decade Counter
When Q1 and Q3 are HIGH together, the counter is cleared by a “glitch” on the CLR line.
CLK Q0
Glitch Q1 Q2 Q3
CLR
Glitch

36. BCD Decoder/Driver
A special-purpose decoder is the This is a BCD-to-seven segment display with active LOW outputs.
VCC
BCD/7-seg
The a-g outputs are designed for much higher current than most devices (hence the word driver in the name).
BI/RBO
BI/RBO
BCD inputs
Outputs to seven segment device LT LT
RBI
RBI
74LS47
GND

37. BCD Decoder/Driver
Here the 7447 is an connected to an LED seven segment display. Notice the current-limiting resistors, required to prevent overdriving the LED display.

38. 7447 BCD-to-7-Segment Decoder/Driver
4 input pins for BCD code.
7 output pins to control the seven segments of a 7-segement display.
Also has a lamp test input.
Also a ripple-blanking input and output to suppress leading or trailing zeroes.
Data sheet: 7447
-Follow link for pin-out and logic symbol.

39. Review: Asynchronous versus Synchronous Counters
4-bit Asynchronous Counter (also called ripple counter):
4-bit Synchronous Counter: 39

40. Synchronous Counters
In a synchronous counter all flip-flops are clocked together with a common clock pulse. Synchronous counters overcome the disadvantage of accumulated propagation delays, but generally they require more circuitry to control states changes.
This 3-bit binary synchronous counter has the same count sequence as the 3-bit asynchronous counter shown previously.
HIGH Q0
Q0Q1 Q0 Q1 Q2 J0 J1 J2 C C C K0 K1 K2
CLK

41. A 4-bit Synchronous Binary Counter
The 74LS163 is a 4-bit IC synchronous counter with additional features over a basic counter. It has parallel load, a CLR input, two count enables, and a ripple count output that signals when the count has reached the terminal count.
Data inputs D0 D1 D2 D3
CLR
LOAD
ENT
RCO
ENP
CLK
Example waveforms are on the next slide… Q0 Q1 Q2 Q3
Data outputs

42. Data inputs Data outputs CLR LOAD D0 D1 D2 D3 CLK ENP ENT Q0 Q1 Q2 Q3
RCO
Count Inhibit
Clear Preset

43. Some Synchronous Counter ICs
74160 and 74162: Four-bit synchronous decade counters (MOD 10)
These two are the same as each other except that has asynchronous clear, while has synchronous clear.
74161 and 74163: Four bit synchronous binary counters (MOD 16)
These two are the same as each other except that has asynchronous clear, while has synchronous clear.
-LOAD is synchronous on all.
-Do Practice Question 11.
-Datasheet incorrectly shows clock as negative edge-triggered on ‘160, ‘161, ‘162, and ‘163, but correctly shows it as positive edge-triggered on LS versions.

44. Up/Down Synchronous Counters
Data inputs
Data outputs
MAX/MIN
CLK Q0 Q1 Q2 Q3
LOAD
CTEN
RCO
D/U D0 D1 D2 D3 C
CTR DIV 10
74HC190
The 74HC190 is a high speed CMOS synchronous up/down decade (MOD-10) counter with parallel load capability. It also has a active LOW ripple clock output (RCO) and a MAX/MIN output when the terminal count is reached.
Data inputs
Data outputs
MAX/MIN
CLK Q0 Q1 Q2 Q3
LOAD
CTEN
RCO
D/U D0 D1 D2 D3 C
CTR DIV 16
74HC191
The 74HC191 has the same inputs and outputs but is a synchronous up/down binary (MOD-16) counter.

45. Some Up/Down Synchronous Counter ICs
74190 Four bit up/down decade counter (MOD 10)
74191 Four bit up/down binary counter (MOD 16)
-Note that LOAD is asynchronous.
-Do Practice Question 12.

46. Cascading Counters
Most counter chips are 4-bit counters, with a modulus of 16 or less.
To get larger moduli, you cascade two or more counter chips together.
When you cascade counters, their moduli multiply, not add.
Example: If you cascade a MOD-10 counter with a MOD-16 counter, you get a MOD-160 counter.
The connections for cascading counters differ depending on whether you’re using asynchronous counters or synchronous counters. 46

47. Cascading asynchronous counters
-What MOD is this counter? 47

48. Cascading Synchronous Counters
For cascading, most synchronous counter chips have one or more enable input pins and one or more terminal-count output pins.
General idea: one chip’s terminal-count output drives the next chip’s enable input. (See next slide).
These pins go by various names such as :
CTEN, CEN, ENT, ENP, for the enable inputs
TC, CO, RCO, MAX, MAX/MIN for the terminal- count outputs.
Also, depending on the chip, these pins may be active-high or active-low. 48

49. Example Solution Cascading synchronous counters
For synchronous IC counters, the next counter is enabled only when the terminal count of the previous stage is reached.
HIGH
CLK Q0 Q1 Q2 C
Counter 1
Counter 2
CTEN
CTR DIV 16 Q3 TC
fin
fout
Explain operation.
Some variations to this basic idea:
-May have more than one enable (‘160).
-Alternate names for enable (ENT, ENP) and TC (RCO, CO, BO) pins.
-Enable and/or TC pins may be active low instead of active-high.
What is the modulus of these cascaded counters?
If fin =100 kHz, what is fout?
Example
Solution
a) Each counter divides the frequency by 16. Thus the modulus is 162 = 256.
b) The output frequency is 100 kHz/256 = 391 Hz 49