1. Computer Organization
Submitted By:
Shaveta Gupta(IT)

2. 3 Fundamental Components of Computer
The CPU (ALU, Control Unit, Registers)
The Memory Subsystem (Stored Data)
The I/O subsystem (I/O devices)
Address Bus
Data Bus
Memory
Subsystem
CPU
Control Bus
I/O Device
Subsystem

3. Each of these Components are connected through Buses.
BUS - Physically a set of wires. The components of the Computer are connected to these buses.
Address Bus
Data Bus
Control Bus

4. Address Bus
Used to specify the address of the memory location to access.
Each I/O devices has a unique address. (monitor, mouse, cd-rom)
CPU reads data or instructions from other locations by specifying the address of its location.
CPU always outputs to the address bus and never reads from it.

5. Data Bus Actual data is transferred via the data bus.
When the cpu sends an address to memory, the memory will send data via the data bus in return to the cpu.

6. Control Bus Collection of individual control signals.
Whether the cpu will read or write data.
CPU is accessing memory or an I/O device
Memory or I/O is ready to transfer data

7. I/O Bus or Local Bus
In today’s computers the the I/O controller will have an extra bus called the I/O bus.
The I/O bus will be used to access all other I/O devices connected to the system.
Example: PCI bus

8. Instruction Cycles
Procedure the CPU goes through to process an instruction.
1. Fetch - get instruction
2. Decode - interperate the instruction
3. Execute - run the instruction.

9. CPU organization CPU controls the Computer
The CPU will fetch, decode and execute instructions.
The CPU has three internal sections: register section, ALU and Control Unit

10. Register Section Includes collection of registers and a bus.
Processor’s instruction set architecture are found in this section.
Non accessible registers by the programmer. These are to be used for registers to latch the address being accessed and a temp storage register.

11. Arithmetic/Logic Unit (ALU)
Performs most Arithmetic and logical operations.
Retrieves and stores its information with the register section of the CPU.

12. MEMORY ORGANIZATION Memory Hierarchy Main Memory Auxiliary Memory
Associative Memory
Cache Memory
Virtual Memory
Memory Management Hardware`

13. Memory
Main memory consists of a number of storage locations, each of which is identified by a unique address
The ability of the CPU to identify each location is known as its addressability
Each location stores a word i.e. the number of bits that can be processed by the CPU in a single operation. Word length may be typically 16, 24, 32 or as many as 64 bits.
A large word length improves system performance, though may be less efficient on occasions when the full word length is not used

14. MEMORY HIERARCHY Memory Hierarchy is to obtain the highest possible
access speed while minimizing the total cost of the memory system
Auxiliary memory
Magnetic
tapes
I/O
Main
processor
memory
Magnetic
disks
CPU
Cache
memory
Register
Cache
Main Memory
Magnetic Disk
Magnetic Tape

15. Memory Subsystem 2 Types of Memory: ROM : Read Only Memory
Program that is loaded into memory and cannot be changed also retains its data even without power.
RAM : Random Access Memory
Also called read/write memory. This type of memory can have a program loaded and then reloaded. It also loses its data with no power.

16. Different ROM Chips Masked ROM : Programmable ROM (PROM) :
ROM that is programmed with data when fabricated. Data will not change once installed. Hardwired.
Programmable ROM (PROM) :
Capable of being programmed by the user with a ROM programmer. Not hardwired.
Erasable PROM (EPROM) :
Much like the PROM this EPROM can be programmed and then erased by light.
EEPROM :
Another form of EPROM but is reprogammable electrically.

17. Different RAM Chips Dynamic RAM (DRAM) : Static RAM (SRAM) :
Leaky capacitors. Caps are charged and slowly leak until they are refreshed to there original data locations. Ex. Computer RAM
Static RAM (SRAM) :
Much like a register. The contents stay valid and does not have to be refreshed. SRAM is faster than DRAM but cost more Ex. Cache
Each RAM chip has 2^n * m. n address inputs and m bidirectional data pins

18. The operation of cache memory
Main
Memory
(DRAM)
CPU
Cache
(SRAM)
= Bus connections
1. Cache fetches data from next to current addresses in main memory
2. CPU checks to see whether the next instruction it requires is in cache
3. If it is, then the instruction is fetched from the cache – a very fast position
4. If not, the CPU has to fetch next instruction from main memory - a much slower process

19. Addressing Modes Immediate Direct Indirect Register Register Indirect
Displacement (Indexed)
Stack 2

20. Immediate Addressing Operand is part of instruction
Operand = address field
e.g. ADD 5
Add 5 to contents of accumulator
5 is operand
No memory reference to fetch data
Fast
Limited range 3

21. Immediate Addressing Diagram
Instruction
Opcode
Operand 4

22. Direct Addressing Address field contains address of operand
Effective address (EA) = address field (A)
e.g. ADD A
Add contents of cell A to accumulator
Look in memory at address A for operand
Single memory reference to access data
No additional calculations to work out effective address
Limited address space 5

23. Direct Addressing Diagram
Instruction
Opcode
Address A
Memory
Operand 6

24. Direct Addressing Diagram
Instruction
Opcode
Address A
Memory
Operand 6

25. Indirect Addressing (1)
Memory cell pointed to by address field contains the address of (pointer to) the operand
EA = (A)
Look in A, find address (A) and look there for operand
e.g. ADD (A)
Add contents of cell pointed to by contents of A to accumulator 7

26. Indirect Addressing (2)
Large address space
2n where n = word length
May be nested, multilevel, cascaded
e.g. EA = (((A)))
Draw the diagram yourself
Multiple memory accesses to find operand
Hence slower 8

27. Indirect Addressing Diagram
Instruction
Opcode
Address A
Memory
Pointer to operand
Operand 9

28. Register Addressing (1)
Operand is held in register named in address filed
EA = R
Limited number of registers
Very small address field needed
Shorter instructions
Faster instruction fetch 10

29. Register Addressing (2)
No memory access
Very fast execution
Very limited address space
Multiple registers helps performance
Requires good assembly programming or compiler writing
N.B. C programming
register int a;
c.f. Direct addressing 11

30. Register Addressing Diagram
Instruction
Opcode
Register Address R
Registers
Operand 12

31. Register Indirect Addressing
C.f. indirect addressing
EA = (R)
Operand is in memory cell pointed to by contents of register R
Large address space (2n)
One fewer memory access than indirect addressing 13

32. Register Indirect Addressing Diagram
Instruction
Opcode
Register Address R
Memory
Registers
Pointer to Operand
Operand 14

33. Displacement Addressing
EA = A + (R)
Address field hold two values
A = base value
R = register that holds displacement
or vice versa 15

34. Displacement Addressing Diagram
Instruction
Opcode
Register R
Address A
Memory
Registers
Pointer to Operand +
Operand 16

35. Relative Addressing A version of displacement addressing
R = Program counter, PC
EA = A + (PC)
i.e. get operand from A cells from current location pointed to by PC
c.f locality of reference & cache usage 17

36. Base-Register Addressing
A holds displacement
R holds pointer to base address
R may be explicit or implicit
e.g. segment registers in 80x86 18

37. Indexed Addressing A = base R = displacement EA = A + (R)
Good for accessing arrays
R++ 19

38. Stack Addressing Operand is (implicitly) on top of stack e.g.
ADD Pop top two items from stack and add 21

39. Input-Output Organization
11-1 Peripheral Devices
I/O Subsystem
Provides an efficient mode of communication between the central system and the outside environment
Peripheral (or I/O Device)
Input or Output devices attached to the computer
11-2 Input-Output Interface
1) A conversion of signal values may be required

40. 2) A synchronization mechanism may be needed
The data transfer rate of peripherals is usually slower than the transfer rate of the CPU
3) Data codes and formats in peripherals differ from the word format in the CPU and Memory
4) The operating modes of peripherals are different from each other
Each peripherals must be controlled so as not to disturb the operation of other peripherals connected to the CPU
Interface
Special hardware components between the CPU and peripherals
Supervise and Synchronize all input and output transfers

41. Transfer
Synchronous Data Transfer
All data transfers occur simultaneously during the occurrence of a clock pulse
Registers in the interface share a common clock with CPU registers
Asynchronous Data Transfer
Internal timing in each unit (CPU and Interface) is independent
Each unit uses its own private clock for internal registers

42.    
Fig Source-initiated strobe
Fig Destination-initiated strobe

43. Fig. 11-5 Source-initiated handshake    
Handshake : Agreement betwee  
Fig Source-initiated handshake
Fig Destination-initiated handshake

44. 11-4 Modes of Transfer 1) Programmed I/O 2) Interrupt-initiated I/O
Data transfer to and from peripherals
1) Programmed I/O
2) Interrupt-initiated I/O
3) Direct Memory Access (DMA)
4) I/O Processor (IOP)
Interrupt-initiated I/O
1) Non-vectored : fixed branch address
2) Vectored : interrupt source supplies the branch address (interrupt vector)

45. Identify the highest-priority source by software means
Polling
Identify the highest-priority source by software means
One common branch address is used for all interrupts
Program polls the interrupt sources in sequence
The highest-priority source is tested first
Polling priority interrupt
If there are many interrupt sources, the time required to poll them can exceed the time available to service the I/O device
따라서 Hardware priority interrupt
Daisy-Chaining :
“1”
“0”

46. One stage of the daisy-chain priority arrangement : Fig. 11-13   
INTACK
INT
One stage of the daisy-chain priority arrangement : Fig
 No interrupt request
 Invalid : interrupt request, but no acknowledge
 No interrupt request : Pass to other device (other device requested interrupt )
 Interrupt request

47. Direct Memory Access (DMA)
DMA controller takes over the buses to manage the transfer directly between the I/O device and memory

48. 2) Cycle stealing transfer DMA Initialization Process
Transfer Modes
1) Burst transfer :
2) Cycle stealing transfer
DMA Controller ( Intel 8237 DMAC )
DMA Initialization Process
1) Set Address register :
memory address for read/write
2) Set Word count register :
the number of words to transfer
3) Set transfer mode :
4) DMA transfer start :
5) EOT (End of Transfer) :

49. 1) I/O Device sends a DMA request 2) DMAC activates the BR line
DMA Transfer (I/O to Memory)
1) I/O Device sends a DMA request
2) DMAC activates the BR line
3) CPU responds with BG line
4) DMAC sends a DMA acknowledge
to the I/O device
5) I/O device puts a word in the data
bus (for memory write)
6) DMAC write a data to the address
specified by Address register
7) Decrement Word count register
8) Word count
9) Word count register

50. Input-Output Processor (IOP)
Communicate directly with all I/O devices
Fetch and execute its own instruction
IOP instructions are specifically designed to facilitate I/O transfer
DMAC must be set up entirely by the CPU
Designed to handle the details of I/O processing

51. Memory units acts as a message center :
CPU - IOP Communication
Memory units acts as a message center :
each processor leaves information for the other

52. Input/output Devices
Input/output devices are required for users to communicate with the computer.
In simple terms, input devices bring information INTO the computer and output devices bring information OUT of a computer system. These input/output devices are also known as peripherals.

53. Input Devices are: Keyboard Mouse Joystick Scanner Light Pen
Touch Screen

54. \ Output devices are:
Printers
Plotters
Monitor
LCD

55. Intel 8086/8088 Microprocessors
Intel 8086 and 8088 Microprocessors are the basis of all IBM-PC compatible computers (8086 introduced in 1978, first IBM-PC released in 1981)
All Intel, AMD and other advanced microprocessors are based on and are compatible with the original 8086/8
At Power Up and Reset time, Pentiums, Athlons etc all look like 8086 processors

56. Intel 8086/8088 Microprocessors
Intel 8086 is a 16b microprocessor:
16b data registers, 16b ALU
Width of external data bus:
8086: 16b
8088: 8b
Width of external address bus: 16b+4b=20b
Some techniques to optimise the CPU performance when it’s executing programs
Segment: Offset memory model
Little-Endian Data Format

57. 8086/8088 Original IBM PC used 8088 microprocessor
8088 is similar to the 8086, but it has an external 8b data bus & only 4B-deep queue
For cost reduction reasons
We can consider 8086 and 8088 together
PC clones often used 8086 for better performance
8-bit bus reduces performance, but meant cheaper computers

58. 8086/8088 Functional Units

59. 8086/8088 8086/8088 consists of two internal units
The execution unit (EU) - executes the instructions
The bus interface unit (BIU) - fetches instructions, reads operands and writes results
The 8086 has a 6B prefetch queue
The 8088 has a 4B prefetch queue

60. 8086/8088 Internal Organisation

61. BIU Elements
Instruction Queue: the next instructions or data can be fetched from memory while the processor is executing the current instruction
The memory interface is slower than the processor execution time so this speeds up overall performance 
Segment Registers:
CS, DS, SS and ES are 16b registers
Used with the 16b Base registers to generate the 20b address
Allow the 8086/8088 to address 1MB of memory
Changed under program control to point to different segments as a program executes
Instruction Pointer (IP) contains the Offset Address of the next instruction, the distance in bytes from the address given by the current CS register

62. 8086/ bit Addresses

63. BIU Elements
Instruction Queue: the next instructions or data can be fetched from memory while the processor is executing the current instruction
The memory interface is slower than the processor execution time so this speeds up overall performance 
Segment Registers:
CS, DS, SS and ES are 16b registers
Used with the 16b Base registers to generate the 20b address
Allow the 8086/8088 to address 1MB of memory
Changed under program control to point to different segments as a program executes
Instruction Pointer (IP) contains the Offset Address of the next instruction, the distance in bytes from the address given by the current CS register

65. 8086/8088 Summary First Generation (introduced June 1978)
One of the first 16b processors on the market
16b internal registers
16/8b external data bus
20b address bus (1MB addressable)
Used in 1st generation IBM PCs (1981)

66. Thanks