1. Update on analog design for L4-L5
SVT confcall – 14/10/11
Polimi design team:
Luca Bombelli (Postdoc)
Bayan Nasri (PhD since 1st October)
Paolo Trigilio (Master student since 1st October)
Stefano Facchinetti (PhD, at LBL till end 2011)
Carlo Fiorini A

2. Mid-term program of Polimi activities
evaluation of requirements for FE design for L4-L5
noise evaluation vs. processing time for FE design for L4-L5 with IBM technology with detector parameters
(basically to align with Lodovico’s estimations of 18/03/11)
requirements for digitalization (ADC/TOT) and solution choice.
start of design or preamplifier and filter

3. Few preliminary questions
resolution of 0.2MIP over the range of 15MIPs: constant or variable along the range? Impact on decision of ADC (6-7 bits) or TOT (3-4 bits). Effect of compression on S/N. S/N ratio of 20 mentioned in specs.
efficiency of 95% for not pile-up events, no problem if the other pile-up events are not rejected?
noise model of resistance Rs of microstrip
Power supply: 1.2 V, with ± 10 mV tolerance (on-chip voltage regulators and maybe a DC-DC converter are needed) 10mV maybe optimistic, strategy?
Signal polarity: the same chip for p and n readout. Same preamplifier with inversion (programmable) before the shaper?