1. Common Readout Unit (CRU) workshop CERN 08-10 Mars 2016
Readout Chain Muon Identifier 08Mar2016 REGIONAL crate upgrade  ()
ALICE
Common Readout Unit (CRU) workshop
CERN Mars 2016
07-Mar-2016 v1
Subatech, IN2P3/CNRS-l’UNAM, Nantes, F44307, France Ch. Renard, J.-L. Béney, P. Pichot, Alice-Muon-Trigger-Upgrade

2. Readout Chain Muon Identifier Actual Muon Trigger readout chain
2x 8 REGIONAL crates
Actually, Muon-Trigger readout chain contains two times height REGIONAL crates.
07-Mar-2016 v1
Subatech, IN2P3/CNRS-l’UNAM, Nantes, F44307, France Ch. Renard, J.-L. Béney, P. Pichot, Alice-Muon-Trigger-Upgrade

3. Readout Chain Muon Identifier Actual Muon Trigger readout chain
VME J1 backplane
Custom J2 backplane
Custom J3 backplane
Each REGIONAL crate contains one REGIONAL card, sixteen LOCAL cards and three backplanes names J1, J2 and J3.
1 REGIONAL card
16 LOCAL cards
07-Mar-2016 v1
Subatech, IN2P3/CNRS-l’UNAM, Nantes, F44307, France Ch. Renard, J.-L. Béney, P. Pichot, Alice-Muon-Trigger-Upgrade

4. ALICE MUON ARM @SUBATECH-Elec xxMar2016 Service Electronique  (maintenance MTR)
VME J1 backplane
VME J2 backplane
1 VME proc
Custom J3 backplane
Each REGIONAL crate contains one REGIONAL card, sixteen LOCAL cards and three backplanes names J1, J2 and J3.
1 JTAG card
1 GLOBAL card
1 FET card
2 DARC cards
07-Mar-2016 v1
Subatech, IN2P3/CNRS-l’UNAM, Nantes, F44307, France Ch. Renard, J.-L. Béney, P. Pichot, Alice-Muon-Trigger-Upgrade

5. Readout Chain Muon Identifier REGIONAL crate upgrade (goal)
Trig
ACQ
det contr
Fpga
LOCAL card (*16)
128*front end
1*local tracklet
(clk40+Din+Dout)
1*I²C (SDA +SCL)
config (reset, card-position)
power
LOCAL with 128 LVDS inputs, 1 1 I²C, 1 FPGA, 1 LVDS output, 1 LHC-clock, 8x8 delay switch, power, config, USB3.0
8*8*delay switch
1*USB (32bit)
16*local tracklet
(clk40+Din+Dout)
power
J2 back plane
config (reset, 16*card-position)
config (reset, crate#)
J2 with 16 LVDS lines, I²C, power, config, 1-to-16 USB3.0 hub
1*USB3.0 slave
16*USB3.0 master
16*I²C (SDA +SCL)
16*I²C (SDA +SCL)
USB >16 hub
Trig
ACQ
det contr
Fpga
REGIONAL card
REGIONAL with 16 LVDS inputs, GBTx, 2 GBT-SCA, 2 GBT 1 FPGA, 1 LVDS output, power, config, USB3.0, 1-to-2 USB3.0 hub
VTRx
GBTx
(clk40+Din+Dout)
GBT SCA
8*I²C
(SDA +SCL)
1*regional tracklet
16*local tracklet
(clk40+Din+Dout)
config (reset, crate#)
power
LVDS buff
1*I²C (SDA +SCL)
1*USB (32bit)
For the upgrade, we will keep almost the same organisation: One REGIONAL card, sixteen LOCAL cards but only a custom J2 backplane.
07-Mar-2016 v1
Subatech, IN2P3/CNRS-l’UNAM, Nantes, F44307, France Ch. Renard, J.-L. Béney, P. Pichot, Alice-Muon-Trigger-Upgrade

6. Readout Chain Muon Identifier REGIONAL crate upgrade (data format)
At each e-link input in CRU
Coding of heartbeat event in LOCAL
Number of bits
Coding of physics (self triggered) event in LOCAL
Coding of heartbeat event in REGIONAL
Coding of physics (self triggered) event in REGIONAL
START BIT (always '1') LOCAL BUSY ('0'=OK; '1'=FIFO full) LOCAL DECISION (tracklet) CARD TYPE (always '1'=LOCAL) HEARTBEAT (always '1') ACQUISITION ('0'=OFF; '1'=ON) ("11"=RST; "10"=EOR; "01"=SOR; "00"=other)
START BIT (always '1') LOCAL BUSY ('0'=OK; '1'=FIFO full) LOCAL DECISION (tracklet) CARD TYPE (always '1'=LOCAL) HEARTBEAT (always '0') ACQUISITION (always '1'=ON) Free bits (always '0')
START BIT (always '1') REGIONAL BUSY ('0'=OK; '1'=FIFO full) REGIONAL DECISION (tracklet) CARD TYPE (always '0'=REGIONAL) HEARTBEAT (always '1') ACQUISITION ('0'=OFF; '1'=ON) ("11"=RST; "10"=EOR; "01"=SOR; "00"=other) 2
START BIT (always '1') REGIONAL BUSY ('0'=OK; '1'=FIFO full) REGIONAL DECISION (tracklet) CARD TYPE (always '0'=REGIONAL) HEARTBEAT (always '0') ACQUISITION (always '1'=ON) Free bits (always '0')
LOCAL bunch counter (~1.6ms) 16
REGIONAL bunch counter (~1.6ms)
LOCAL board position in crate (0-15) 4
REGIONAL crate number (0-15)
Status: "0xF"
Data: Non zero detector plane(s) (1 bit / word)
Status: Masks on tracklet inputs
Data: Non zero tracklet inputs
Status: Masks on inputs [(X4, Y4), (X3, Y3), (X2, Y2), (X1, Y1)]
32*4
Data: Non zero strip pattern(s) [(X4, Y4), (X3, Y3), (X2, Y2), (X1, Y1)]
32*i (i=0 to 4)
N/A
Total number of bits
32*5
32*i (i=2 to 5) 32
number of bunch needed to send 20
8 to 20
07-Mar-2016 v1
Subatech, IN2P3/CNRS-l’UNAM, Nantes, F44307, France Ch. Renard, J.-L. Béney, P. Pichot, Alice-Muon-Trigger-Upgrade

7. Readout Chain Muon Identifier REGIONAL crate upgrade (heartbeat [1])
CRU
Code sent by CRU to FEE
REGIONAL
LOCAL
FRONT END TEST
SOR Prepare
Update internal Orbit and BCID counters
Transmit command to all e-links
Reset event buffers
Start assembling events
0x80
Reset internal bunch counter
Reset acquisition FIFO
Start writing into acquisition FIFO (First event = status)
SOR
Start sending events
N/A
EOR Prepare
0x40
Stop writing into acquisition FIFO (Last event = status)
EOR
Stop assembling events
Stop sending events
PAUSE
0x20
RESUME
0x10
CALIBRATE
0x08
Send LVDS pulse to Front-End cards
DUMP
0x04
Write one event = status into acquisition FIFO
RESET
0x02
Stop writing into acquisition FIFO
CLOSE TIMEFRAME
Send NEW TIMEFRAME event
0x01
SYNC
[1] O2 Project CWG4. Proposal of an Heartbeat trigger for ALICE Run 3. Technical report, The ALICE Collaboration, 2013
07-Mar-2016 v1
Subatech, IN2P3/CNRS-l’UNAM, Nantes, F44307, France Ch. Renard, J.-L. Béney, P. Pichot, Alice-Muon-Trigger-Upgrade

8. Readout Chain Muon Identifier REGIONAL crate upgrade (DCS)
CRU (x1? X2?)
REGIONAL (x16)
LOCAL (x256)
FRONT END TEST (x1) r- ID
Date
Status Rw
Config
mask
Mask rw
GBTx0 status
GBTx status
GBTx1 status
07-Mar-2016 v1
Subatech, IN2P3/CNRS-l’UNAM, Nantes, F44307, France Ch. Renard, J.-L. Béney, P. Pichot, Alice-Muon-Trigger-Upgrade

9. Readout Chain Muon Identifier REGIONAL crate upgrade (prototype)
Trig
ACQ
det contr
Fpga
LOCAL part
7*local tracklet
(clk40+Din+Dout)
7*I²C (SDA +SCL)
config (reset, card-position)
1*USB (8bit)
MID_PROTO card
Trig
ACQ
det contr
Fpga
REGIONAL part
1*regional tracklet
7*local tracklet
VTRx
GBTx
(clk40+Din+Dout)
GBT SCA
7*I²C
(SDA +SCL)
(clk40+Din+Dout)
config (reset, crate#)
LVDS buff
1*I²C (SDA +SCL)
1*USB (8bit)
Quartz 40MHz
2*card clock
Roboclock 1->8
JTAG mux
power
“LOCAL” with I²C, 1 FPGA, 7 LVDS output, config, USB (8bit)
“REGIONAL” with 7 LVDS inputs, 9 1 GBTx,1 GBT-SCA, 8 I²C, 1 GBT 1 FPGA, 1 LVDS output, config, USB (8bit)
07-Mar-2016 v1
Subatech, IN2P3/CNRS-l’UNAM, Nantes, F44307, France Ch. Renard, J.-L. Béney, P. Pichot, Alice-Muon-Trigger-Upgrade

10. Readout Chain Muon Identifier REGIONAL crate upgrade (prototype)
JTAG mux
1 REGIONAL card
Up to 7 LOCAL cards in one FPGA
VTRx
GBT-SCA
GBTx
07-Mar-2016 v1
Subatech, IN2P3/CNRS-l’UNAM, Nantes, F44307, France Ch. Renard, J.-L. Béney, P. Pichot, Alice-Muon-Trigger-Upgrade

11. Readout Chain Muon Identifier REGIONAL crate upgrade (prototype)
Ongoing simulations
Parts to test
Tools needed
Results
Comments/Next steps
Simulate response of MID_PROTO_LOC to heartbeat triggers (SYNC, SOR, EOR, RESET)
ALTERA Quartus Prime 15.
ModelSim-Altera 10,4b
Latest fpga_mid_proto_local Firmware
Latest fpga_mid_proto VHDL testbench
OK 22 December 2015
Simulate response of MID_PROTO_LOC to FEE data with zero suppression
ALTERA Quartus Prime 15.1 programmer
Simulate reception of MID_PROTO_LOC data in CRU
Simulate response of MID_PROTO_LOC to USB slow-control read
OK 18 January 2016 But some compilations disconnect the input data of bidir bus
Find a way to fix the effect of compilation
Simulate response of MID_PROTO_REG to heartbeat trigger (SYNC, SOR, EOR, RESET)
Latest fpga_mid_proto_regional Firmware
Simulate response of MID_PROTO_REG to FEE data with zero suppression
Simulate reception of MID_PROTO_REG data in CRU
Simulate response of MID_PROTO_REG to USB slow-control read
07-Mar-2016 v1
Subatech, IN2P3/CNRS-l’UNAM, Nantes, F44307, France Ch. Renard, J.-L. Béney, P. Pichot, Alice-Muon-Trigger-Upgrade

12. Readout Chain Muon Identifier REGIONAL crate upgrade (prototype)
Ongoing tests
Parts to test
Tools needed
Results
Comments/Next steps
Download Firmware into JTAG_SWITCH (ALTERA® MAX®V: 5M160ZT100C5) FPGA
ALTERA Quartus Prime 15.1 programmer
ALTERA® USB-Blaster
Latest fpga_mid_proto_mux_jtag file
OK 21 January 2016
Download Firmware into MID_PROTO_LOC (ALTERA® Cyclone®V: 5CEBA7F31C7) FPGA
JTAG_SWITCH FPGA
Latest fpga_mid_proto_mux_local file
OK 01 February 2016
Download Firmware into MID_PROTO_LOC (ALTERA® EPCQ64SI16N) EEPROM
Latest fpga_mid_proto_mux_regional file
Failed 21 January 2016
Try again without protection diodes and capacitors
Download Firmware into MID_PROTO_REG (ALTERA® Cyclone®V: 5CEBA7F31C7) FPGA
Download Firmware into MID_PROTO_REG (ALTERA® EPCQ64SI16N) EEPROM
Configure FTDI® (FT240X) USB to serial chip
FTDI® “FT Prog” 3.0 software
OK 24 February 2016
Recognised as USB-Blaster by ALTERA Quartus Prime 15.1 programmer
Configure FTDI® (FT2232HLT) USB to dual FIFO chip
FTDI® “FT Prog” 1.12 software
Open link to USB-to-FIFO interface (local part)
National-Instruments® LabVIEW® 2011
mid_proto_test.vi
OK 02 February 2016
Open link to USB-to-FIFO interface (regional part)
Read ID register in MID_PROTO_LOC FPGA
Failed 02 February 2016
Spy with ALTERA® SignalTap tool and/or oscilloscope
Read ID register in MID_PROTO_REG FPGA
Generate configuration file for the GBTx
GBT team web page
OK 25 August 2015
Install configuration Software from GBT team
Local configuration of the GBTx
GBTx I²C address: 0x1
USB-to-I²C dongle from GBT team
Configuration Software from GBT team
Configuration file generated from GBT team web page
Failed 10 February 2016
See image next slide
Talk with GBT team
07-Mar-2016 v1
Subatech, IN2P3/CNRS-l’UNAM, Nantes, F44307, France Ch. Renard, J.-L. Béney, P. Pichot, Alice-Muon-Trigger-Upgrade

13. Readout Chain Muon Identifier REGIONAL crate upgrade (prototype)
GBTx configuration
07-Mar-2016 v1
Subatech, IN2P3/CNRS-l’UNAM, Nantes, F44307, France Ch. Renard, J.-L. Béney, P. Pichot, Alice-Muon-Trigger-Upgrade

14. Readout Chain Muon Identifier REGIONAL crate upgrade ()
STATUS
Firmware simulated in VHDL testbench
continuous readout
heartbeat triggers
USB slow-control
Embedded USB-Blaster validated
USB slow-control not working yet
Started inquiry with SignalTap
GBTx not configured yet
Will be happy to use a C-RORC as testbench
07-Mar-2016 v1
Subatech, IN2P3/CNRS-l’UNAM, Nantes, F44307, France Ch. Renard, J.-L. Béney, P. Pichot, Alice-Muon-Trigger-Upgrade