1. TEACHING CMOS CIRCUIT DESIGN IN NANOSCALE TECHNOLOGIES USING MICROWIND
Etienne Sicard
Professor
Department of Electrical & Computer Engineering
INSA – University of Toulouse - France
Web site:

2. ZOOM AT INTEGRATED DEVICES TEACHING ISSUES EDUCATIONAL NEEDS MICROWIND
SUMMARY
CONTEXT
ZOOM AT INTEGRATED DEVICES
TEACHING ISSUES
EDUCATIONAL NEEDS
MICROWIND
4. EVALUATION
5. APPLICATION NOTES
6. PERSPECTIVES
7. CONCLUSION

3. INCREASED INTEGRATED CIRCUIT COMPLEXITY
CONTEXT
INCREASED INTEGRATED CIRCUIT COMPLEXITY
2004
130nm
100M
Core+ DSP
1 Mb Mem
2006
90nm
250M
Core DSPs
10 Mb Mem
2008
45nm
500M
Dual core
Dual DSP RF
Graphic Process.
100 Mb Mem
Sensors
2010
32nm 2G
Quad Core
Quad DSP
3D Image Proc
Crypto processor
Reconf FPGA,
Multi RF
1 Gb Memories
Multi-sensors
22nm
2012 7G
5nm
150 G
2020 ?
Technology
Complexity
Packaging
Embedded blocks

4. INCREASED SWITCHING PERFORMANCES
CONTEXT
Tri-Gate for increasing drive current and reducing leakage
INCREASED SWITCHING PERFORMANCES
High K Metal Gate to increase field effect
90 nm
Strain to increase mobility
Current drive (mA/µm)
2.0
1.5
Gate material
1.0
Strain
0.5
Intrinsic performances
0.0
130 nm
65 nm
45 nm
32 nm
22 nm
17 nm
Technology node

5. DECREASED VOLTAGES AND NOISE MARGIN
CONTEXT
DECREASED VOLTAGES AND NOISE MARGIN
500 mV
margin
100 mV
margin
Supply (V)
5.0
3.3
I/O supply
2.5
Core supply
1.8
1.2
Tension cœur: réduire la puissance consommée, fragilité des oxyde
Tension I/O: reduction => aller + vite de 0 à VDD, mais – rapide pour des raison de compatibilité entre techno
1.0
0.5µ
0.35µ
0.18µ
130n
90n
65n
45n
32n
22n
17n
Technology
Adapted from ITRS roadmap for semiconductors, 2011
November 17

6. ZOOM AT INTEGRATED DEVICES
SYSTEM TO INTEGRATED CIRCUITS
10 mm
100 mm
November 17

7. 10µm
Integrated Circuits…
1mm
1 µm
100 nm
© Intel Xeon
November 17

8. THE OLD TIMES - SO SIMPLE
TEACHING ISSUES
THE OLD TIMES - SO SIMPLE
One supply
No option
2 metal layers
nMOS
pMOS

9. THE OLD TIMES – MOS MODEL 1
TEACHING ISSUES
THE OLD TIMES – MOS MODEL 1
5 parameters

10. NANO-CMOS – SO MANY NEW THINGS
TEACHING ISSUES
NANO-CMOS – SO MANY NEW THINGS
2 supply
Low K
Double patterning
Metal gate
nMOS Strain
Pocket implant
pMOS Strain
High K oxide
8 Metal
Double gates

11. TEACHING ISSUES
NANO-CMOS – BSIM4 MODEL

12. NANO-CMOS – BSIM4 MODEL TEACHING ISSUES
Only 20 most important paramaters are implemented
Full BSIM4 model: over 200 parameters for one MOS device

13. NANO-CMOS – SO MANY OPTIONS
TEACHING ISSUES
NANO-CMOS – SO MANY OPTIONS 1 10
100
1000
500
1500
Ion (µA/µm)
Ioff (nA/µm)
Parasitic
consumption
High (x 10)
Moderate
(x 1)
Low
(x 0.1)
Speed
Fast
(+50%)
(0%) ( -
50%)
High
end
servers
Servers
Networking
Computing
Mobile
Consumer
3G phone s
2G phones
MP3
Digital camera
speed
General
Purpose
Low leakage
Personal org.
« Super high speed »
« Super low leakage »

14. COMPLEXITY CHALLENGE TEACHING ISSUES
Teaching physical design – still necessary ?
Link
Controller RF RS
Host
Interface
Code
Manager
Complexity
(Millions transistors)
Technology
always ahead
1000
System design
IP design
100
Logic design 10
Microwind
Layout design 1
0.1
1995
1998
2001
2004
2007
2010
2013

15. TEACHING NANO-CMOS – TRENDS
EDUCATIONAL NEEDS
TEACHING NANO-CMOS – TRENDS
Physics
CMOS design
Teaching hours
System integration
Years
Embedded software
The commercial chip design tools available today are very powerful
However, these tools are highly complex and need long time to learn.
Teaching hours in Nano-CMOS are decreased
Physics of semiconductors are exploding in complexity ( parameters in MOS models)
Student and engineer diversity must be considered. Gaps in the background knowledge must be addressed

16. TEACHING NANO-CMOS – NEEDS
EDUCATIONAL NEEDS
TEACHING NANO-CMOS – NEEDS
Professional
tools
Graduates
Undergraduates
PhDs
Educational
Short
sessions :
Simple design
Concepts
Long practical
Ambitious designs L
arge number of students
Reduced number of
students
Tools should be used by large number of students at undergraduate level
Design tools should provide intuitive design, simulation and visualization environments
Design tools should be easily accessible. Most of the work is done out of regular teaching hours (e-learning, project-based..)
Target course and practical training duration: 15 H
Target level : Master year 1
Learning curve
Hours
Industry -
oriented
tools
Education
oriented tools
Rapid
progress 5 10 15 20 S
low

17. COURSE CONTENTS (1-2 days)
MICROWIND
COURSE CONTENTS (1-2 days)
Technology scale down, where we come from, where we are (45 nm), where we go..
A tutorial on MOS devices, based on problem- based learning
The design of inverters, and a simple ring oscillator, and a small student contest.
The design of basic logic gates introducing interconnect design, compact design strategies, and impact on switching speed and power consumption.
The design of analog blocs introducing amplification, voltage reference, addition of analog signals, and mixed-signal blocs
A design project, e.g. converter, processing unit, OpAmp, radio-frequency block, etc..

18. INTRODUCTION THE TOOL MICROWIND
User-friendly and intuitive design tool for educational use.
The student draws the masks of the circuit layout and performs analog simulation
The tool displays the layout in 2D, static 3D and animated 3D

19. MICROWIND 1. 2.
MOS DEVICE
Traditional teaching : in-depth explanation of the potentials, fields, threshold voltage, and eventually the expression of the current Ids
Our approach : step-by-step illustration of the most important relationships between layout and performance.
Design of the MOS
I/V Simulation
2D view
Time domain analysis 4. 3.

20. BASIC GATE DESIGN MICROWIND 2.
Illustration of the most important relationships between layout and performance.
Design of pMOS
Design of inverters
Design of a VCO
Try to optimize the VCO for highest possible speed
Improve MOS size
Change MOS options
Make the layout more compact
Keep an eye on power consumption 2. 1. 4. 3.

21. PROJECT EXAMPLES MICROWIND 2.
engage students in a stimulating learning experience using latest CMOS technologies
Circuit analysis and optimization using WinSpice
Combinational and sequential circuit layouts
ALU Design
Power amplifier Bluetooth 2. 1. 3. 4.

22. EVALUATION
AUDIENCE #
Question 1
I have a clear idea of what is expected of me in this course. 2
The ways in which I was taught provided me with opportunities to pursue my own learning. 3
The course enabled me to develop and/or strengthen a number of the qualities of a [University of South Australia,INSA] graduate. 4
I felt there was a genuine interest in my learning needs and progress. 5
The course developed my understanding of concepts and principles 6
The workload for this course was reasonable given my other study commitments 7
I have received feedback that is constructive and helpful. 8
The assessment tasks were related to the qualities of a [University of South Australia, INSA] graduate. 9
The staff teaching in this course showed a genuine interest in their teaching. 10
Overall I was satisfied with the quality of this course
The VLSI course was evaluated anonymously by the students
UNISA course evaluation questionnaire containing ten core questions and open text response.
The students rated the course very highly in all the evaluation items.
The course in the in the top-5 courses offered in engineering in UniSA.
(off-line: Dr. Aziz won the “top teacher of the year” in Australia 2009)

23. 5. The course developed my understanding of concepts and principles
EVALUATION
RESULTS
Answers to questionnaire
UNISA
5. The course developed my understanding of concepts and principles
INSA

24. STUDENT REPORTS ON-LINE
EVALUATION
STUDENT REPORTS ON-LINE
The best student reports are put on-line on > Student reports
Student works from other institutes and countries are also placed on-line

25. EVALUATION COMMENTS Teachers Students
“The tools along with the project-based course resources have assisted us to develop an educational program in our Bachelor of Engineering Program. The tools offer easy to use menus for design and simulation, and the choice of a range of technology models to enable students to develop critical design and analysis skills using the latest technologies.” (Malaysia).
“Microwind and Dsch tools are used for VLSI teaching programs at both postgraduate and undergraduate levels. The project-based methodology supported by a variety of learning resources has made the learning of VLSI Design very stimulating.” (Bangladesh).
“Exploring the tools is a lot of fun. The interface is very friendly, and the program is both educational and useful for designing CMOS chips.” (USA)
Teachers
Students
“From just a few logic gates, we have created a 4-stage binary counter and compiled it into layout. It also gave us the basic concepts to understand the operation of the transistors in order to extract their models.”
“The 24-hours clock project was a good exercise which permitted us to see how it is inside a semiconductor and how it works.”
“We learned a lot about designing integrated circuit. We faced some practical problems, and tried to solve them or to understand them.”
“This study allows us to understand the DAC running. In spite of some design problems, we managed to make the DAC work well.”
“Before doing this project, we hadn’t thought that there are as many ways to realize an amplifier. It’s an area not easy to understand. Each technique has its limit. We tried to optimize our operational amplifier design to maximize the gain.”

26. INTRODUCING TECHNOLOGY NODES
APPLICATION NOTES
INTRODUCING TECHNOLOGY NODES
Application notes on 90, 65, 45 & 32nm technologies
Evolution of MOS devices and interconnect performances
Synthesis of the state of the art (Intel, Samsung, ST- microelectronics, ITRS…)
Illustration and discussion on technology advances

27. INTRODUCING NEW ISSUES
APPLICATION NOTES
INTRODUCING NEW ISSUES
Ion/Ioff trend including random I/V device performances
Process variability implemented in Microwind,

28. MICROWIND USED IN 50+ SCIENTIFIC PAPERS
APPLICATION NOTES
MICROWIND USED IN 50+ SCIENTIFIC PAPERS
2011
A CMOS VLSI implementation of Mean Life Time(MLT) Detector for Bio-luminescence Sensor
4-Bit Fast Adder Design Topology and Layout with Self-Resetting Logic for Low Power VLSI Circuits
AREA EFFICIENT 3.3GHZ PHASE LOCKED LOOP WITH FOUR MULTIPLE OUTPUT USING 45NM VLSI TECHNOLOGY
Flip-Flop Circuit Families:Comparison of Layout and Topology for Low Power VLSI Circuits
Low-Area Low-Power and High-Speed TCAMS
POWER EFFICIENT DESIGN OF COUNTER ON .12 MICRON TECHNOLOGY
Design and Performance Analysis of 5 GHz CMOS RF Front-End Circuits for IEEE a Application
DESIGN AND DEVELOPMENT OF ANALOG TO DIGITAL CONVERTER USING DIFFERENTIAL RING OSCILLATOR
Design and test challenges in Nano-scale analog and mixed CMOS technology
Layout Design of a 2-bit Binary Parallel Ripple Carry Adder Using CMOS NAND Gates with Microwind
A NOVEL DESIGN FOR HIGHLY COMPACT LOW POWER AREA EFFICIENT 1-BIT FULL ADDERS
Area, Delay and Power Comparison of Adder Topologies
Comparative Analysis of 7T and 6T SRAM Using 0.18μm Technology
COMPARATIVE ANALYSIS OF ENERGY-EFFICIENT LOW POWER 1-BIT FULL ADDERS AT 120NM TECHNOLOGY
2012
Comparative Analysis of Low Power 4-bit Multipliers Using 120nm CMOS Technology
COMPARISON AMONG DIFFERENT CMOS INVERTER WITH STACK KEEPER APPROACH IN VLSI DESIGN
Comparison of Transistor count Optimized Full adders with modified CMOS Full adders
Design and Analysis of Low Power Full Adder Using Adiabatic Technique
Design and Performance of CMOS Circuits in MICROWIND
Design of a Low Power Flip-Flop Using MTCMOS Technique
Design of a Multiplexer In Multiple Logic Styles for Low Power VLSI
Designing and Analysis of 8 Bit SRAM Cell with Low Subthreshold Leakage Power
Implementation of LFSR Counter using CMOS Chip Technology
Leakage Power Reduction in CMOS VLSI Circuits
Novel keeper technique for Domino logic circuits in DSM Technology
Ultra Wideband Low Noise Power Amplifier
Low Power 8T Column Decoupled Sram Cell with Bit Line Decoupled Current Mode Sense Amplifier
Interconnect Analysis of a Novel Multiplexer Based Full-Adder Cell for Power and Propagation Delay Optimizations
Journals and Conferences
International Journal of Engineering Science and Technology
IEEE Int’l Conf. on Computer & Communication Technology
IEEE International Conference on Recent Trends in Information,
Telecommunication and Computing
IEEE Trans Education
International Conference on Electrical and Computer Engineering ICECE
International Journal of VLSI design & Communication Systems
International Journal of Engineering Research and Applications
International Journal of Computer Applications
International Journal of Soft Computing and Engineering
European Journal of Scientific Research
World Journal of Science and Technology
International Journal of Advances in Engineering & Technology
International Journal of Emerging Technology and Advanced Engineering
International Conference on Emerging Frontiers in Technology for Rural Area
Microelectronics Journal
International Journal of Modern Engineering Research
World Academy of Science, Engineering and Technology

29. SPPORT LATEST TECHNOLOGY ADVANCES
PERSPECTIVES
SPPORT LATEST TECHNOLOGY ADVANCES
Application notes on 22 nm and 17 nm technologies
Introduction of FinFET device
Introduction to 3D-IC technology & design

30. CONCLUSION
Intuitive and user friendly design tools enabled students to develop circuit design skills using nano-CMOS technologies
Illustrations (2D, 3D, I/V) help to handle increased process complexity and refinements
Effective project-based learning methodologies, helping to understand the impacts of technology scale down on factors such as speed, power and noise.
Digital and analog basic bloc design with high levels of student satisfaction.
Projects stimulate student curiosity and thinking.
Software to be tuned to 22 nm technology, FinFET and 3D
Microwind successfully used at Master level, also cited in research papers

31. The tool, manual and course slides are online at
REFERENCES
E. Sicard and S. Ben Dhia “Basic CMOS Cell Design” McGraw Hill professional series, 2006.
E. Sicard and S. Ben Dhia “Advanced CMOS Cell Design” McGraw-Hill professional series, 2007.
E. Sicard, “Microwind & Dsch User's Manual, Version 3.5”, June Online at
S. M. Aziz, E. Sicard, S. Ben Dhia “Effective Teaching in Physical Design of Integrated Circuits using Educational Tools” IEEE Trans Education, Nov. 2010
The tool, manual and course slides are online at

32. REFERENCES
MICROWIND DOWNLOADS (NI2Designs, India)

33. THANK YOU FOR YOUR ATTENTION MERCI POUR VOTRE ATTENTION www. microwind
THANK YOU FOR YOUR ATTENTION MERCI POUR VOTRE ATTENTION