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XC5200 Series A low cost gate array alternative Gate Array

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Presentation on theme: "XC5200 Series A low cost gate array alternative Gate Array"— Presentation transcript:

1 XC5200 Series A low cost gate array alternative Gate Array
The XC5200 was introduced in 1995 as Xilinx’ most cost-effective FPGA family. Although additional process, design, and test improvements have allowed the Spartan Series to offer similar costs but with RAM and higher speed, the XC5200 offers many unique features and will be supported for years to come. A low cost gate array alternative

2 XC5200 FPGA Family Up to 23,000 gates 50MHz system performance
Robust feature set Unlimited reprogrammability Pin-Locking Flexibility: VersaRing 5 Volt Devices The XC5200 family offers relatively low densities and speeds for FPGAs, and is limited to a 5V family. The low cost makes it an attractive replacement for older gate arrays, and the family is pin-compatible with the XC4000 families.

3 XC5200 Series Features Gate array replacement success since 1995
World’s fastest 5V FPGA volume ramp A low cost FPGA/gate array alternative Low cost, process-optimized architecture XC5200 Family: 5V, 0.5m High performance with robust feature set - Carry Logic - 3-state buffers - Cascade Chain - 4 Global Nets - JTAG Logic - Slew rate control Xilinx introduced this series in 1995, and achieved resale of 1 million units faster than any FPGA in history. The 5-V XC5200 family is produced on a 0.5 micron, 3-layer metal (TLM) process, providing the -3 speed grade.

4 XC5200 Architecture Overview
Architecture Highlights: VersaBlockTM logic module VersaRingTM I/O interface General Routing Matrix (GRM) The next several slides provide an overview of the unique architecture of the XC5200 family. This top-level view shows the overall structure. The CLB common to most Xilinx FPGAs is combined with local routing to create a VersaBlock. The GRM functions like a Programmable Switch Matrix, connecting the channel routing. Significant additional routing for the I/Os is called the VersaRing.

5 Abundant VersaBlock Routing
VersaBlock equals: Configurable Logic Block (CLB) 4 identical Logic Cells 4 3-state buffers Local Interconnect Matrix (LIM) 100% local connectivity Up to 23 in, 8 out Direct Connects Result: abundant local routing Minimizes routing congestion Granular and symmetrical We are now zooming in to a single VersaBlock. The LIM is routing dedicated to the CLB itself. With such a large CLB, with 20 inputs and 12 outputs, large functions can be accomplished without having to use the channel routing.

6 XC5200 Configurable Logic Block
Configurable Logic Block (CLB) 4 Identical Logic Cells 20 inputs, 12 outputs 2 5-input functions Logic Cell (LC0 - LC3) Function generator, register, & control logic Independently usable F & FD Programmable flip-flop or latch Fast carry logic or cascade chain Independent feed-through We are now zooming in further to look at the CLB part of the VersaBlock. It is composed of four identical cells, which exactly match the definition of a Logic Cell - a four-input lookup table and a storage element.

7 XC5200 Carry Logic: 4-bit Adder
carry out This shows the implementation of a four-bit adder. Since the XC5200’s carry logic is much simpler than that in the XC4000 or Spartan Series, it requires two levels of logic. However, direct interconnect is easily used to propagate to the second level, making the implementation very fast and efficient.

8 XC5200 Cascade Chain: 16-bit Decoder
Fast implementation of wide input functions Adjacent CY_MUXes connect to provide cascadable decode logic Flexible LUT allows general decode, AND and OR cascade chains The path used for the serial propagation of the carry can also be used to cascade a Boolean result and make a 16-input gate in one CLB.

9 XC5200 Family Efficient 5-Input Functions
Allows any combination of 2 separate 5-input functions in one CLB LC0 and LC1 and/or LC2 and LC3 combined with F5_MUX Unified Library support: F5MAP or F5_MUX Efficient 4:1 muxes Any two five-input functions can be built by using the F5_MUX, which was not shown in the previous slides.

10 Optimizing 5-Input Functions
- or - Five input AND using F5_MUX Five input AND using F5MAP The F5_MUX can be called out explicitly, or a MAP symbol can be added to any 5-input function to force the use of the F5_MUX. Both schematics will result in identical implementations

11 Implementing 4:1 MUX using F5_MUX
Allows 4:1 muxes in 1/2 CLB The F5_MUX can also implement some 6-input functions, such as a 4:1 mux, in just 1/2 of the CLB.

12 Abundant Routing Resources
Local Interconnect Matrix 6 Levels of Hierarchy General Routing Matrix 10 single length lines 4 double length lines 8 longlines per channel VersaBlock Local Interconnect Matrix Direct connects to all neighbors Logic cell feedthrough Single Length Lines Now that we’ve looked at the VersaBlock, we can quickly look at the other two types of resources, the routing and the I/O cells. The six types of routing resources provide metal segment s of varying lengths, allowing the tools to make the best speed tradeoffs. Double Length Lines Direct Connects Longlines

13 XC5200 Global Line Network 4 global clock buffers
Direct access to all CLB clock pins (CK) Access to non-clock pins via GRM Buffers can be sourced by IOB or internal routing The 4 global clock buffers drive 4 global lines that are available to all registers.

14 XC5200 TBUF Connectivity Four TBUFs/CLB
Any CLB output can drive any TBUF “Weak-keeper” circuit maintains previous state No pull-ups; use cascade chain for wired functions The XC5200 three-state buffers can be used to enable one of several signals onto a long line, acting as a multiplexer. They cannot be used as a Wired-AND as in the XC4000 family.

15 VersaRingTM: High Utilization AND Pin Assignment Flexibility
Versatile interface between internal logic and I/O I/O decoupled from core logic Incremental edge routing VersaRing resources 8 horizontal/vertical longlines 4 direct connects in/out 4 double length lines to GRM 10 single length lines to GRM 8 single length lines to adjacent VersaRing tile Significant additional routing along the perimeter simplifies pin-locking.

16 XC5200 Input / Output Block Selectable input, output or 3-state
Optional pull-up / pull-down Dedicated boundary scan logic 8 mA output sink & source current 4 global nets Programmable slew rate control Programmable input delay line The I/O block is very simple, with no storage elements. This allows the I/Os to be packed closer together, providing a more efficient die size even with a high ratio of I/Os to logic cells.

17 100% Footprint Compatibility in Common Packages
XC5200 Family XC5202 XC5204 XC5206 XC5210 XC5215 Max Logic Gates 3,000 6,000 10,000 16,000 23,000 Typical Gate Range 2-3K 4-6K 6-10K 10-16K 15-23K Logic Cells ,296 1,936 Flip-Flops ,296 1,936 Max I/O Performance -6/-5/-4/-3 -6/-5/-4/ /-5/-4/ /-5/-4/ /-5/-4/-3 Packages: VQ64 PC84 PC84 PC84 PC84 PQ/VQ100 PQ/VQ100 PQ/VQ100 TQ144 TQ144 TQ144 TQ144 PQ160 PQ160 PQ160 PQ160 TQ176 TQ176 PQ208 PQ208 HQ208 PQ240 HQ240 PG156 PG156 PG191 PG223 The family includes five devices, from 3,000 to 23,000 max logic gates (2,000 to 15,000 typical). 100% Footprint Compatibility in Common Packages

18 XC5200 Success Since 1994 XC5200 support to year 2005 and beyond
2.5M Revenue Units High Volume Design Wins Digital camera add-in card Cable modem Set-up box Video game CD player Graphics add-in card 10/100 Mbit Ethernet add-in cards The XC5200 was one of Xilinx’ fastest growing FPGA families, and is used in high-volume production in a number of designs made possible by its low cost. 4Q94 2Q96 2Q97 XC5200 support to year 2005 and beyond

19 XC5200 Series shipping NOW in High Volume Markets
XC5200 Series Success Market Application Volume Consumer-Video Set-Top-Box 150,000 units Consumer-Audio High-end CD Player 25,000 units Consumer-Video Video Game 50,000 units Data Processing PC Add-in Card 250,000 units Data Processing Display Monitor 100,000 units Communication PCS Base Station 25,000 units Communication Modem Card 100,000 units Communication Voice Mail 50,000 units Automotive Shock Absorber Control >100,000 units The XC5200 family was the first low-cost, full-featured FPGA family. Today, the XC5200 and Spartan families open up whole new application areas for FPGAs. XC5200 Series shipping NOW in High Volume Markets

20 Xilinx XC5200 vs. Altera Flex 6K
XC5200 Advantages Segmented interconnect Lower power Five XC5200 devices vs. three 6K devices More features (flip-flop clock enables, cell feed-through, VersaRing, VersaBlock, etc.) Altera Flex 6K is a poor copy of the innovative XC5200 architecture The Altera FLEX 6K family offers a similar idea, with no RAM or I/O flip-flops as a way of reducing cost. The FLEX 6K family offers only one 5V device, along with 3 3V devices. Xilinx’ segmented interconnect and wide range of densities offers important advantages over the FLEX 6K. For designs requiring higher speed, the Xilinx Spartan Series surpasses the FLEX 6K at a similar cost.

21 Logic Cell Comparison Feature XC5200 Flex 6K Clock Enable Yes No
Direct Feed-through Yes No Independent Logic & Flip-flop Outputs Yes No Clocks per Flip-flop 1:4 2:10 Logic Cells Per Block 4 10 Also, the Altera FLEX 6K does not offer the key features that are needed for a complex FPGA solution.

22 XC5200 Benefit Summary Feature Benefit Robust System Level Features:
Process Optimized - Small die size Architecture - Unlimited reprogrammability Up to 50MHz performance VersaRingTM I/O - Pin assignment flexibility Interface - Flexibility to change logic without requiring PCB relayout 100% Footprint - Easy density migration within family Compatibility Robust System Level Features: - Fast Carry Logic - High speed arithmetic functions Dedicated JTAG logic - Eases system-level testability - 3-state buffers - Efficient on-chip bussing Cascade chain - Efficient wide-input functions The XC5200 offers a complete set of system-level features at low cost.

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