1. Thermal Aware EM Computation
Imran qureshi Kartik Iyer
Implementation
Motivation
Example - Design:
1 Kbyte SRAM array
1read / 1 write port
Lots of control logic
Run Time Statistics
Power EM
14mins
Signal EM
31mins
∆T calc.
24mins
Total
69mins
Design Statistics
Size
210 X 13sq.um
No. of Domains
6 (5 power, 1 Ground)
Node Count
1 M
Resistor Count
Planar >> FinFET Migration Challenges:
Higher drive strength >> Increase power density
3D FIN structures and increased wire density >> Poor Heat dissipation
Thinner wires >> Reduced EM limits
Traditional Methodology >> Worst case Temperature EM sign-off >> Too pessimistic 
Proposed Methodology >> Thermal aware EM sign-off  >> Accurate and
faster design closure 
TEMPERATURE MAP
Thermal Aware EM Computation Methodology
CTM-based Thermal and wire Self-heat
calculation with thermal coupling
Wire Self-heat
Report
Thermal Profile /
Back-annotation
Totem
Chip Thermal Model (CTM) (Avg current) Iavg per wire
Signal wire Irms
Power EM Run
Signal EM Run
Tech file & Dev Models
GDS
DSPF
w/ Signal RC
Foundry SH
Input
Simulation o/p
& xml file
All the word-lines were having ΔT greater than 10 degrees
Some sections were having 19 degrees ΔT
Traditional Methodology vs Selfheat flow
Delta-T calculation (Self-heat components)
Self heat-induced ∆T
on BEOL
Thermal coupling among BEOL
Wire Temp for
Thermal-aware EM Analysis
Joule heating
Wire-Wire coupling
∆T coupling from FEOL
Device-Wire coupling
Temp Profile from CTM-based thermal
Chip Base Temperature
Summary
Device & Wire self-heating >> Big concern in FinFET technology nodes
Thinner interconnect & Tighter margins >> Over design for reliability >> Time for design closure increases
Thermal aware EM computation >> Accounts for device & wire-self heating effects >> Thermally accurate EM results
Scalable methodology >> Standard cells to complex Analog macros
Methodology further extended >> Determine junction temperature >> Accounting chip power density & ambient temperature conditions >> optimize the block placements, heat sink placements,etc
𝚫 𝑻 𝒇𝒊𝒏𝒂𝒍 =𝑪𝒉𝒊 𝒑_𝑩𝒂𝒔𝒆 𝒕𝒆𝒎𝒑 + 𝚫 𝑻 𝒋𝒐𝒖𝒍𝒆_𝒉𝒆𝒂𝒕𝒊𝒏𝒈 +𝚫 𝑻 𝒅𝒆𝒗𝒊𝒄𝒆_𝒘𝒊𝒓𝒆_𝒄𝒐𝒖𝒑𝒍𝒊𝒏𝒈 +𝜟 𝑻 𝒘𝒊𝒓𝒆_𝒘𝒊𝒓𝒆_𝒄𝒐𝒖𝒑𝒍𝒊𝒏𝒈