1. Benefits and Challenges of 40-nm Process Technology

2. Compromises of the Past
FPGAs
High density and high performance OR low power
ASICs versus
FPGAs
Low cost OR flexibility and time to market
Latest technology
Earliest access to 40-nm technology OR low-risk path to production
Productivity
High performance,
high logic
utilization OR fast compile time

3. Introducing Altera’s 40-nm Solutions
Stratix® IV
FPGAs
Highest density,
highest performance AND lowest power
HardCopy® IV ASICs
Benefits of FPGAs AND benefits of ASICs
Foundry
partnership
Earliest access to
40-nm technology AND low-risk path
to production
Quartus® II software
Highest performance, highest logic utilization, AND fastest compile times

4. Partnering With TSMC on 40-nm Development
Altera and TSMC continue 15-year partnership
A competitive edge for TSMC, Altera, and their customers
Created leading-edge 40-nm process
Employs 193-nm immersion photolithography, strained silicon, and extreme low-k material
Accelerated development methodology
Process co-development
Reuse of core technologies
Enhanced test chip methodology
Allows for industry’s fastest time to advanced processes
Earliest access to 40-nm technology AND low-risk path to production 4

5. In 40 nm, we convert benefits of strain to lower power
40-nm Process
40 nm is a major investment in technology for Altera and TSMC
Major component of 40-nm process is second-generation strained silicon
Strain engineering offers significant
transistor performance
Increases electron and hole mobility by up to 30%
Transistor level performance is up to 40% higher
The benefits of strained silicon
(performance) can be converted to:
Higher speed
Lower power (standby and dynamic)
Or a combination of both
NMOS
PMOS
Allowed us to use 0.9V core voltage (reduces power consumption) V^2 and keep same performance. Question: Is there a 40nm core voltage standard? Are we following it?
In 40 nm, we convert benefits
of strain to lower power

6. Design Methodology for “First Silicon to Production”
Leading-class performance
Innovative power reduction techniques
Accurate transistor models enabling optimum device performance
Leading-class reliability
Built-in redundancy techniques
Built-in design for manufacturability
Built-in design for reliability
Silicon validation through test chips
Concurrently providing high-performance and low-risk devices to customers

7. Silicon Validation Through Test Chips
Test chips combined with process modeling and simulations are the foundation of “first silicon to production”
Test chip goal:
De-risk the product against process and circuit design uncertainties
Validate innovative process improvements and circuit design techniques
Optimize tradeoffs for performance and manufacturability
Test chips and design refinements:
Internal iterations prior to product tape out
Final
implementation
Concept
Refinement
Margin
Proof
Test chip 1
SPICE v0.1
Test chip N
SPICE v1.0
Test chip process reduces risk for the customer

8. Test Chips 9 test chips prior to the 1st product tape out in 90 nm
Results:
First silicon to production on all 90-nm devices
On-time delivery on all 90-nm devices
First tape out to customer shipment in less than 3 months for 65 nm
An Altera® 40-nm test chip

9. Stratix IV FPGAs: A Closer Look
Highest density
Up to 680K logic elements (LEs)
Up to 22.4-Mbits internal RAM
Up to 1, x 18 multipliers
Highest bandwidth and performance
Up to 48 transceiver blocks operating up to 8.5 Gbps
Up to 4 x8 hard intellectual property (IP) blocks for PCI Express Gen1 and Gen2
Up to 748 giga multiply-accumulate operations per second (GMACS) digital signal processing (DSP) performance
2 speed-grade performance advantage
Lowest power
Programmable Power Technology
Quartus II PowerPlay technology
40-nm process benefits including 0.9V core voltage
Seamless FPGA prototyping to HardCopy ASIC production
Quartus II software v8.0: #1 in performance and productivity
Highest density, highest performance, AND lowest power

10. Stratix IV FPGA Device Family Plan
LEs
Transceivers
(8.5, 3.2 Gbps1)
LVDS
I/Os
Memory (Mbits)
Multipliers (18x18)
Stratix IV GX
device
EP4SGX70
70K
8 (8,0) 28
368
6.3
384
EP4SGX110
110K
16 (16,0)
8.1
512
EP4SGX230
230K
36 (24,12) 88
736
13.9
1,288
EP4SGX290
290K
13.3
832
EP4SGX360
360K
864
17.7
1,040
EP4SGX530
530K
48 (32,16) 98
904
20.3
1,024
Stratix IV E
EP4SE110 - 56
480
EP4SE230
EP4SE290
12.4
EP4SE360
EP4SE530
112
960
EP4SE680
680K
132
1,104
22.4
1,360
Notes: 1) Full duplex serial transceivers
2) Details on roadmap to faster speed transceivers available upon request 10 10

11. Stratix IV GX Device Package Plan
F780
(29 mm)
F1152
(35 mm)
F1517
(40 mm)
F1932
(45 mm)
EP4SGX70
368, 28, 8
EP4SGX110
368, 28, 16
EP4SGX230
1st rollout device
560, 44, 16
560, 44, 24
736, 88, 36
EP4SGX290
288, 0, 16
864, 88, 36
EP4SGX360
EP4SGX530
2nd rollout device
904, 98, 48
Details subject to change
Pin migration
Total I/O, LVDS, transceiver counts
Notes: Flip chip ball-grid array (BGA) with 1.0-mm pitch 11 11

12. Stratix IV E Device Package Plan
F780
(29 mm)
F1152
(35 mm)
F1517
(40 mm)
F1760
(43 mm)
Stratix III
device
EP3SL200
864, 88
EP3SE260
960, 112
EP3SL340
1,104, 132
Stratix IV
EP4SE110
480, 56
EP4SE230
EP4SE290
736, 88
EP4SE360
EP4SE530
EP4SE680
Details subject to change
Notes: Flip chip ball-grid array (BGA) with 1.0-mm pitch
LVDS I/O count represents full duplex channels and are included in the total I/O count

13. Unprecedented Transceiver Bandwidth
350
Innovation zone
300
250
200
Transceiver bandwidth (Gbps)
150
100 50
Transceivers available
on both sides
100
200
300
400
500
600
Devices
kLEs
Stratix II GX
Stratix IV GX
Virtex-5 LXT
Virtex-5 SXT
Virtex-5 FXT
Up to 320-Gbps full-duplex bandwidth
Up to 32 transceivers operating from 600 Mbps to 8.5 Gbps
Up to 16 additional transceivers operating from 600 Mbps to 3.2 Gbps
Up to 4 x8 PCI Express Gen1, Gen2 hard IP at 2.5/5.0 Gbps

14. Altera’s Transceiver Innovations
Enhanced quad transceiver blocks
Additional configurable 5th and 6th full-duplex channels
Channel bonding up to 24 channels including support for SFI-5 and HyperTransport™ 3.0 protocols
Dynamic reconfiguration
Run-time reconfiguration of transceiver settings, data rates, and protocols
Hitless for adjacent channels
Tremendous flexibility allows universal front ends
Less board and software variations
Identical HardCopy IV GX transceiver block
Unprecedented system bandwidth AND superior signal integrity

15. Excellent 40-nm Transceiver Test Chip Results
Pattern: PRBS 7
Vod: 600 mV
DJ: 10.3 ps
RJ (RMS): 1.23 ps
Excellent jitter performance
Low-risk path to production
Watch the demo video at
8.5 Gbps

16. Robust Transceiver System Design
8.5-Gbps transceivers with superior signal integrity
Jitter compliance for PCI Express, CEI-6, and SONET/synchronous digital hierarchy (SDH) with margin
Ability to drive 50” of FR-4 backplane at Gbps with built-in pre-emphasis and equalization
Plug & Play Signal Integrity, only from Altera
Monitors and optimizes receive equalization over process, voltage, and temperature (PVT)
Supports hot swapping of transceivers
Watch the demo video to see Plug & Play Signal Integrity in action at

17. Protocol Support 17 Protocol HardCopy IV ASICs Stratix IV FPGAs
3G protocols
PCI Express Gen1 (x1, x2, x4, x8), PCI Express Cable 
Serial RapidIO® (1x, 4x)
Gigabit Ethernet, XAUI (IEEE 802.3ae), HiGig+
3G basic (proprietary), 3G SerialLite II
CPRI v3.0, OBSAI v2.0/RP3-01 v4.0
SONET OC-3/12/48, GPON
SATA, SAS
SD, HD and 3G SDI, ASI
Serial Data Converter (JESD204)
SFI 5.1
Up to 8 channels
HyperTransport 3.0
6G protocols
PCI Express Gen2 (x1, x2, x4, x8)
HiGig2, CEI 6G (SR/LR), Interlaken, DDR-XAUI, SPAUI
6G basic (proprietary), 6G SerialLite II
6G CPRI/OBSAI
Fibre Channel (FC1/FC2/FC4) 17 17

18. Hard IP for PCI Express Benefits
Pre-verified, complex IP cores
x8, x4, x2, x1 PCI Express Base rev 2.0 compliant core (includes rev 1.1) supporting a rootport and endport function
Integrated transaction layer (TL), data link layer (DLL), physical interface/media access control (PHY/MAC), and transceivers
2.5 Gbps (Gen1) and 5 Gbps (Gen2) per lane
Device cost reduction
Fit designs in a smaller FPGA
Resource savings
Up to 25K LEs (x8 Gen2 configuration)
Embedded memory buffers
Replay buffer
Receive buffer (per virtual channel)
Power savings relative to soft IP core implementations
Shorter design and compile times

19. Highest Performance Memory Interfaces
Altera innovations enable DDR3 at 1,067 Mbps/533 MHz
Smart interface module with PVT auto-calibration
Dynamic on-chip termination significantly saves power
Example: 1.0W on a 72-bit I/F with a 50/50 read/write cycle
Plenty of memory bandwidth to support next-generation applications:
416 Gbps (333 MHz), 463 Gbps (400 MHz), 556 Gbps (533 MHz)
1:2
multiplex
DQ hard I/O
Sync
block
Read
Sync
block
Write
Dynamic
on-chip
termination
Programmable output drive strength and slew rate control
Variable delay for dynamic trace compensation
Read/write leveling and resynchronization capability

20. Stratix III/IV I/O Performance
Stratix III/IV FPGAs
Interconnect
Performance
DDR3
533 MHz/1,067 Mbps
DDR2
400 MHz/800 Mbps
QDR II
350 MHz
QDR II+
400 MHz
RLDRAM II
LVDS
1.6 Gbps
I/O feature
Stratix III/IV FPGAs
Benefit
Dynamic on-chip termination 
Saves power
DDR3 read/write leveling
DIMM support
Variable I/O delay
Allows signal de-skew
Up to 24 I/O banks distributed on all sides offer more flexibility 20 20 20

21. Core Fabric Innovation
High-bandwidth interfaces combined with a high-density, feature-rich, and high-performance core fabric
More than twice the density
530K LEs on Stratix IV GX FPGAs and 680K LEs on Stratix IV E FPGAs
Embedded memory
Up to 20.3/22.4 Mbits (GX/E)
Performance at 600 MHz
Optimized for efficiency and internal memory bandwidth
DSP
Up to 1,288/1, x 18 multipliers (GX/E)
Performance at 550 MHz
1,600
Innovation zone
1,400
1,200
1,000
Number of 18x18 Multipliers
800
600
400
200
100,000
200,000
300,000
400,000
500,000
600,000
700,000
800,000
Density (LEs)
Stratix III L FPGA
Stratix III E FPGA
Stratix IV E/GX
FPGA
Virtex-5 LX/LXT
Virtex-5 SXT
Virtex-5 FXT

22. TriMatrix Embedded Memory
Dual-port RAM, error correction coding (ECC), low-power mode
Memory functions
Stratix IV devices
Memory
Processor code storage
Packet buffers
External memory I/F cache
Video frame buffers
16–64 M144K (2,048 x 72 bits)
600 MHz
General-purpose memory
462-1,280 M9K (256 x 36 bits)
Shift registers
Small FIFO buffers
Filter delay lines
50 percent of the logic can be turned into an MLAB
M144K
144K bits
M9K
9K bits
MLAB
640 bits
Optimized size for optimal memory/logic ratio and maximum memory bandwidth

23. Clocking Resources Flexible and robust clocking resources
Global clock networks
Clock routing resources
16 global clock networks (GCLK)
Up to 88 quadrant clock networks (QCLK)
Up to 132 periphery clock networks (PCLK)
Global clock routing can also be used for global signals
Powered down when not in use
Full-featured and robust PLLs
Up to 12 low-jitter PLLs
10 programmable outputs per PLL
Both frequency and phase can be dynamically changed
Cascadable to allow broader frequency generation
16 networks per device
Regional clock networks
Up to 88 networks per device
Flexible and robust clocking resources
to support higher system integration

24. Architecture Optimized for Performance
Reg
Adder 1 2 3 4 5 6 7 8
ALM inputs
ALM
Comb.
Logic -
input
fracturable LUT
Two 3
adders
Two registers
logic i
Most advanced FPGA architecture
Adaptive logic modules (ALMs) perform logic operations in less time
Multi-track routing
Ability to implement wide high-performance buses
Reach more logic faster
Efficient, high-performance data passing through the system
Number of reachable ALMs
Benefit
Hops
Stratix IV FPGA
Virtex-5 FPGA
Stratix IV to Virtex-5 FPGA 1
850
132
6.4X 2
2,400
1,056
2.3X 3
4,000
1,980
2.0X
Total
7,250
3,168

25. Highest Performance on Stratix III/IV FPGAs
1.80
Altera: Stratix III/IV FPGAs
1.60
Xilinx: Virtex-5 FPGAs
35%
1.40
2 speed-grade
advantage
1.20
1.00
Relative FPGA core performance
0.80
0.60
0.40
0.20
0.00
Slow
Medium
Fast
2 speed-grade advantage with
Stratix III/IV FPGAs saves power and cost

26. DSP Performance Through Parallelism72 72
Optimal DSP/memory/ logic ratio
Resources per 18 x 18 multiplier
400 registers
17-Kbit embedded memory
500 LEs
Total 18 x 18 multipliers = 1,360
Maximum clock frequency = 550 MHz
DSP performance = 1,360 * 550 MHz =
748 GMACS

27. Advantages Over Dedicated DSPs
Combination of logic, memory, and multipliers allows for efficient implementation of arithmetic DSP functions
Integrate multiple DSP devices into a single Stratix IV FPGA
Process multiple signal data streams at lower cost per channel than dedicated DSP devices
DSP 20 40 60 80
100
120
140
160
748
210
GMACS
Up to 1,360
multipliers 24
4.8
ADI TS203S
@ 600 MHz
TI C6488
3 cores
@ 1 GHz
Altera EP4SGX70
384 18x18
@ 550 MHz
Altera EP4SE680
1,360 18x18
@ 550 MHz

28. The Significance of Power
Application examples
Challenges
Power supply and board design
Thermal management
Fixed power budgets
Power = cost
Stratix IV FPGAs allow you to integrate more, achieve higher performance with less power
Multiservice provisioning platform (MSPP)
Wireless
basestation
Increase integration and performance while reducing power
Level of integration
Power

29. Save Multiple Watts/Device (200K LEs)
14.000
12.000
10.000
8.000
6.000
4.000
2.000
0.000
Devices
29%
Power (W)
45%
50%
75%
Virtex-5, 1.0V
V5-LX220
Stratix III, 1.1V
EP3SL200
Stratix III, 0.9V
EP3SL200
Stratix IV, 0.9V
EP4SE230
HardCopy IV, 0.9V
HC230
Reduce power consumption—
50% with Stratix IV FPGAS,
75% with HardCopy IV ASICs
Note: Total power is based on 60 percent logic (ALUTs and FFs) at 200 MHz, 25 percent memory utilization of each type of memory, 50 percent DSP 18 x 18 block, 64in/64out 1.8V LVCMOS (200 MHz), 128in/128out 2.5V LVCMOS (200 MHz), 32in/32out (LVDS at 800 MHz), and 72-pin DDR3 interface power savings. 29 29

30. Power Efficiency = Maximum Performance/Watt
40-nm process benefits enable power reduction
Programmable Power Technology
Highest performance where you need it, lowest power everywhere else

31. Stratix IV and HardCopy IV Devices Surpass the Average ASIC Density
Est. avg. gate counts (the Americas)
Stratix/HardCopy gates
Stratix IV FPGA
HardCopy IV ASIC 13 12 11 10 9 8 7
Utilized gates (millions) 6 5 4 3 2 1
2000
2001
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011
Note: Data based on Gartner Dataquest report 11/21/07 31

32. HardCopy IV ASICs: A Closer Look
Seamless prototyping
One design, one register transfer level (RTL), one IP set, one tool delivers FPGA and ASIC implementations
Now with transceivers
Low risk, lowest total cost access to deep sub-micron ASIC benefits
Low power
50 percent or lower than companion FPGA
Guaranteed first-time right
Now with
transceivers
The benefits of FPGAs AND
the benefits of ASICs

33. HardCopy IV Family Device Gates Transceivers Memory (Mbits)
Multipliers (18x18)
HardCopy IV GX
devices
HC4GX1
2.8M 8
6.3
384
HC4GX2
3.9M 16
8.1
512
HC4GX3
9.2M 24
12.2
1,288
HC4GX4
7.6M
12.7
832
HC4GX5
9.5M
13.3
1,040
HC4GX6
11.5M
1,024
HardCopy IV E
HC4E2 -
HC4E3
10.7
HC4E4
HC4E5
16.8
HC4E6
HC4E7
13.3M 33 33

34. Improving Designer Productivity
Issue: High densities require higher levels of productivity
Quartus II software v8.0 is #1 in productivity for high-end FPGAs and HardCopy ASICs
Productivity
Timing
analysis
Compilation speed
Power management
System-level
design
Incremental compilation
PowerPlay
technology
TimeQuest
SOPC Builder 34 34

35. Quartus II Software: A Closer Look
#1 in performance and productivity
3X faster compile times
70 percent further improvement with incremental compilation
TimeQuest timing analyzer
PowerPlay power technology
System-level design
Enhanced SOPC Builder
Advanced DSP Builder
System requirements
Multi-processor support
Lower memory requirements
The only software with integrated support for FPGA and HardCopy ASIC design
Highest performance,
highest logic utilization, AND shortest compile times

36. Stratix IV GX Device Rollout Schedule
EAP ES
Production
EP4SGX230
December 2008
February 2009
June 2009
EP4SGX530
March 2009
April 2009
August 2009
EP4SGX360 NA
October 2009
EP4SGX290
EP4SGX110
September 2009
EP4SGX70
The EAP is Altera’s Early Access Program for selected customers and projects.
Engineering sample (ES) devices are RoHS-compliant by default (leaded ES package by special request). All packages will go to production with both leaded and RoHS-compliant options. 36 36 36

37. Summary Altera is first with 40-nm FPGAs
FPGAs with >2.5 billion transistors
Stratix IV devices sweep the high-end FPGA customer selection scorecard
HardCopy IV ASICs: now featuring high-speed transceivers
Offer seamless prototyping
Quartus II software v8.0: #1 in performance and productivity
Selection criteria
Stratix IV advantage
Density
>2X larger
Transceiver bandwidth
>2X bandwidth (48 XCVRs up to 8.5 Gbps)
Performance
>2 speed-grade advantage (35%)
Memory interface
2 speed advantage (1,067 Mbps)
Power
½ power 37

38. Innovation Without Compromise
40-nm HardCopy IV FPGAs
Innovation Without Compromise

39. Compromises of the Past
Introducing Altera’s 40-nm Solutions
Stratix® IV
FPGAs
Highest density,
highest performance AND lowest power
FPGAs
High density and high performance OR low power
ASICs versus
FPGAs
Low cost OR flexibility and time to market
HardCopy® IV ASICs
Benefits of FPGAs AND benefits of ASICs
Foundry
partnership
Earliest access to
40-nm technology AND low-risk path
to production
Latest technology
Earliest access to 40-nm technology OR low-risk path to production
Quartus® II software
Highest performance, highest logic utilization, AND fastest compile times
Productivity
High performance,
High logic
utilization OR fast compile time

40. HardCopy IV Family System development methodology
Seamless prototyping
Unparalleled productivity—software/hardware co-design and co-verification with fast, easy access to HardCopy ASICs for production
Increased verification (at-speed, in-system)
Low-risk access to ASIC benefits
Low power
Cost effective
Very SEU tolerant
Hard-wired security
Instant-on
Built-in design for manufacturability, design for yield, design for test
Very aggressive 40-nm NRE
Aggressive unit costs
Competitive with standard cell, provided devices are effectively utilized
Fast/predictable turn-around times
Guaranteed first-time right

41. One Design, One RTL, One IP Set, One Tool—Two Implementations
Seamless FPGA prototyping
Fast time to market
Low total cost
Maximum flexibility
SW/HW co-design
HardCopy ASICs for production
Fast time to profit
Low risk
Low power
High performance

42. Ultimate System Development Methodology
Traditional method: Sequential hardware, ASIC, and software development
Traditional ASIC respins stop everything and delay software completion
FPGA flexibility speeds system verification and software development
Saves 9 – 12 months in time to market

43. The Real Story—The Winning Combination
System sooner
Software teams can begin work on the FPGA-based prototype system, knowing the HardCopy ASIC will be compatible
Stratix/HardCopy system development methodology delivers
System better
System cheaper
Software and hardware teams can work together optimizing the architecture, which avoids over-specifying hardware and enables making late changes
No expensive EDA tools are required, no expensive respins are necessary because the verification is far more thorough

44. HardCopy IV Family Plan
HardCopy IV GX ASIC
Device1
FPGA
prototype
6.5+G2
SERDES
I/O
pins
Memory bits (not incl. MLABs)
18x18
multipliers
PLLs
ASIC
gates3
HC4GX1YZ
EP4SGX70
4/8
200 – 368
6.3
384 3
2.8M
HC4GX2YZ
EP4SGX110
4/8/16
8.1
512
3/4
3.9
HC4GX3YZ
EP4SGX230
4/8/16/24
200 – 736
9.8 – 12.2
1,288
3/6/8
9.2M
HC4GX4YZ
EP4SGX290
16/24
256 – 736
10.6 – 12.7
832
7.6M
HC4GX5YZ
EP4SGX360
10.6 – 13.3
1,040
9.5M
HC4GX6YZ
EP4SGX530 24
13.3
1,024
6/8
12.0M
HardCopy IV E ASIC
HC4E2YZ
EP4SE110 -
296 – 480
8.1
512 4
3.9M
HC4E3YZ
EP4SE230
10.7
1,288
9.2M
HC4E4YZ
EP4SE290
392 – 864
12.1 – 13.3
832
4/8/12
7.6M
HC4E5YZ
EP4SE360
480 – 864
16.8
1,040
9.5M
HC4E6YZ
EP4SE530
736 – 880
1,024
8/12
12.0M
HC4E7YZ
EP4SE680
13.3M
Note1: Y = I/O count, Z = package type
Note 2: Performance may increase based on characterization
Note 3: ASIC gates calculated as 12 gates per LE; 5,000 gates per 18x18 multiplier 44 44

45. Spanning the Majority of ASIC Design
Average ASIC start gate density
0.0
5.0
10.0
15.0
20.0
25.0
2000
2001
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011
Millions of gates
Average ASIC logic gates
HardCopy logic gates min.
HardCopy logic gates max.
Note: Data based on Gartner Dataquest report 11/21/07

46. Technical Engagement Process
Tape in
Bring up system with FPGA, prepare design for hand-off
Tape out
Production-quality, fully tested samples
Design center
implementation and verification
Custom mask
Fabrication,
assembly and test
System ready
Sample approval
Production
6 weeks typical
8 weeks typical
~ 3 weeks
12 weeks
Time to samples: 9-14 weeks
Complete flow: as fast as 24 weeks

47. Chronology of HardCopy IV Design Activities
System ready
Design
kick-off
Design
review 1
Design
review 2
Design
review 3
Sample
delivery
Sample
approval
Production
12 weeks(2) typical
6 weeks typical
8 weeks typical
Design development
System bring-up
using FPGA
Prepare design for
final handoff
HardCopy IV back-end
flow in HardCopy Design Center
Custom masks
Sample
fabrication
Assembly and test
Qualify
system
using HardCopy
device
Production
Time
Fully verified FPGA: design hand-off
Tape out
Production-quality,
fully tested samples
Production
units available
Note:
Activities in yellow indicate Altera-controlled schedule
Typical turnaround time (TAT) depends on fab loading – contact Altera for current value;
TAT can be reduced by 2 weeks by payment of additional hot-lot fee

48. Single hand-off turnkey process performed by Altera in 6 weeks typical
Required Tools
HardCopy ASIC
Standard cell ASIC
COT
RTL synthesis
Quartus II software
Third-party EDA
Physical synthesis
Simulation
STA (front end)
Placement and routing (front end)
Pin planning
Power estimation
DFT
Single hand-off turnkey process performed by Altera in 6 weeks typical
ECO-driven flow with numerous hand-offs performed by ASIC vendor in 8 to 26 weeks
STA (back end)
Placement and routing (back end)
Formal verification
Parasitic extraction
LVS/DRC
Typical tool cost
$3K
~$300K
~$1M

49. HardCopy Roadmap Production Customer designs 160+ tape-outs ASIC
Prototype
2001
Hard-wired routes, multi-function I/Os
180 nm
180 nm
HardCopy
APEX
APEX 20K
Hard IP optimization, performance improvement
2003
160+ tape-outs
130 nm
130 nm
Production
HardCopy
Stratix
Stratix
Fine-grained “HCell” architecture, formal verification
2005
90 nm
90 nm
HardCopy II
Stratix II
Improved multi-function I/Os, enhanced HCell architecture, custom packages
2008
40 nm
65 nm
HardCopy III
Stratix III
2008
Customer designs
6.5+ Gbps transceivers
40 nm
40 nm
HardCopy IV E
Stratix IV E
HardCopy IV GX
Stratix IV GX 49 49

50. Application-Optimized Packaging
New approach for cost-sensitive markets
Direct socket replacement—same board, performance-optimized for best combination of performance and signal integrity
1.Package- and pin-compatible
Package-optimized for cost; PCB- and footprint-compatible with FPGA
2. Cost-improved, same PCB
Non-socket replacement—different package, new PCB required
3. Cost-optimized, different PCB

51. What If Your Company Could…
Introduce product 9-12 months earlier?
And implement customer feedback in silicon/software in real time
React to competitive threats and market changes instantaneously?
Using the prototype system to create product variants and mid-life kickers
Create multiple design variations?
Optimizing the function and timing of each

52. A Complete Solution Embedded soft-core Design software processors
SOPC Builder
Advanced DSP Builder
Intellectual
property

53. Ready to learn more?
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54. Safe Harbor
This contains “forward-looking statements” that are made pursuant to the safe harbor provisions of the Private Securities Litigation Reform Act of Forward-looking statements are generally preceded by words that imply a future state or that imply that a particular future event or events will occur such as “will.” Investors are cautioned that all forward-looking statements involve risks and uncertainty, including without limitation the risk that future performance is dependent on product development schedules, the design performance of software and other tools, as well as the company’s and third parties’ development technology and manufacture capabilities. Please refer to the company’s Securities and Exchange Commission filings, copies of which are available from the company without charge.