1. Switcher (SWB) bumping
status report
DEPFET Workshop, Seeon, May 2016
Eva Scheugenpflug, MPG Halbleiterlabor

2. Process: UBM and ball bumping
12/16/2017
Process: UBM and ball bumping
1. ENIG (electroless nickel immersion gold) for UBM
e-Ni plating
Au plating
Fig.1: Schematic of the ENIG process1
2. Solder Ball Jetting
drop balls and reflow
Fig.2: Schematic of the Solder Ball Jetting process1
process installed at PacTech
 qualified with SWB18-v2.0
Nickel:Zincation changes electric potential of Al pad  when immersed in nickel sulfate. Autocatalytic nickel reaction starts
Immersion gold  gold as the more noble metal replaces Ni on the surface
Laser technology was applied to melt a preformed solder ball which was then jetted out of a capillary tube with pressurized inert
gas to form an interconnect on the target circuit. The process combined solder ball bumping and re-flow process into the single
process.
Fig.3: Switcher of SWB18-v2.0 after ball bumping
1Source: PacTech, Dr. Andrew Strandjord et al., „Bumping for WLCSP using Solder Ball Attach on electroless NiAu UBM”
DEPFET Workshop, Seeon, May 2016
Eva Scheugenpflug, MPG Halbleiterlabor
Eva Scheugenpflug, HLL MPG

3. 12/16/2017
UBM process issue
Issue with new SWB version: missing UBM on one particular pad
 difference to other pads: substrate contact
Main differences to SWB18-v2.0:
chip is larger
different passivation
cutting edge (guard ring) exposed
 different electric potential during ENIG process on guard ring and critical pad results in no or different Ni/Au deposition
critical pad
Fig.4: SWB after ENIG process; no Ni/Au on the critical pad
Fig.5: uncoated guard ring on SWB
passivation
guard ring
DEPFET Workshop, Seeon, May 2016
Eva Scheugenpflug, MPG Halbleiterlabor
Eva Scheugenpflug, HLL MPG

4. Process issue solving approaches
Isolate edge with photo resist before the ENIG process
Au-stud instead of UBM
back up process if isolating edge is not successful
process tested at the University of Heidelberg
possibility to do it at HLL
Fig.6: SWB with photo resist (PR) on the long edges
Fig.7: Gold stud2
2Source:
DEPFET Workshop, Seeon, May 2016
Eva Scheugenpflug, MPG Halbleiterlabor

5. Description test 1 Test 1: Coating the long edges of the SWB by hand
preparation of two SWBs:
1. acetone/isopropanol cleaning
2. temperature treatment: 1h, 100°C, under nitrogen
3. mounting on high temperature tape with vacuum tweezer
4. photo resist coating by hand with Q-tip
5. temperature treatment: 1h, 115°C, under nitrogen
 ENIG process at PacTech
Fig.8: SWB with hand-coated photo resist on the long edges
DEPFET Workshop, Seeon, May 2016
Eva Scheugenpflug, MPG Halbleiterlabor

6. Results test 1 ENIG process result for the two SWBs:
Ni/Au thickness on common pads: chip 1: 3-4µm, chip 2: 7µm
Ni/Au thickness on critical pad: chip 1: 1µm, chip 2: 5µm
not able to strip photo resist
resist stripping at HLL
high temperature tape not acetone resistant  single-chip handling
acetone/isopropanol/H2O cleaning
critical pad
Fig.9: chip 1 after ENIG process (x100)
Fig.10: chip 2 after longer ENIG process (x100)
ENIG process works  45 SWBs prepared the same way
DEPFET Workshop, Seeon, May 2016
Eva Scheugenpflug, MPG Halbleiterlabor

7. Results test 1 ENIG process result for the 45 SWBs:
7µm Ni/Au on common pads
5µm Ni/Au on critical pad
photo resist stripping at HLL
critical pad
Fig.11: one representative chip after ENIG process (x100)
Test conclusion: coating by hand
works in principle
BUT too high amount of work (single-chip process for resist coating and stripping)
DEPFET Workshop, Seeon, May 2016
Eva Scheugenpflug, MPG Halbleiterlabor

8. Description test 2
Test 2: Rebuilding of a wafer to get a multi-chip coating process
 280 SBWs on one wafer
opening in the wafer
chip
opening in the PR
Fig.12: wafer with 280 openings
for SWBs
Fig.13: Enlarged section of the wafer: one opening with a SWB (red) in it and the photo resist opening (green) on the SWB
DEPFET Workshop, Seeon, May 2016
Eva Scheugenpflug, MPG Halbleiterlabor

9. Description test 2 Processing steps for multi-chip coating:
laser cutting: openings in the wafer and alignment marks
mounting wafer on the HT (high temperature) tape
put SBWs into wafer openings with vacuum tweezer
lithography
spray coating
exposure
development
temperature treatment (1h, 115°C, under nitrogen)
 Next step: ENIG process at PacTech
DEPFET Workshop, Seeon, May 2016
Eva Scheugenpflug, MPG Halbleiterlabor

10. Results test 2 1 2 3 4 5
Fig.15: SWB 5 in wafer opening
Fig.14: wafer on HT tape with 5 SWBs in the openings
PR coating
preparation of one wafer with 5 SWBs (distributed over the wafer)
Fig.16: SWB 5 in wafer opening after lithography
DEPFET Workshop, Seeon, May 2016
Eva Scheugenpflug, MPG Halbleiterlabor

11. Results test 2 ENIG process result for the wafer with 5 SWBs:
12/16/2017
Results test 2
ENIG process result for the wafer with 5 SWBs:
6-7.5µm Ni/Au on common pads and critical pads
roughness according to contaminations before the ENIG process
Fig.17: SWB 4 after ENIG process
Fig.18: SWB 2 after ENIG process
critical pad
Test conclusion: coating on rebuilt wafer
ENIG process works
ball bumping and shear-tests necessary for final ok
DEPFET Workshop, Seeon, May 2016
Eva Scheugenpflug, MPG Halbleiterlabor
Eva Scheugenpflug, HLL MPG

12. Summary and Outlook
single-chip process for SWB coating by hand successfully tested
multi-chip process for SWB coating with rebuilt wafer installed and successfully tested
ENIG process with coated SWBs successful
 6-7.5µm Ni/Au on common and critical pads
Open issues:
photo resist stripping process
single-chip process (HT tape not acetone resistent)
 tests with new acetone resistant tape from Adwill
ball bumping and shear tests
PacTech is investigating
DEPFET Workshop, Seeon, May 2016
Eva Scheugenpflug, MPG Halbleiterlabor

13. Thank you! DEPFET Workshop, Seeon, May 2016
Eva Scheugenpflug, MPG Halbleiterlabor