1. Computer Organization Authors: Carl Hamacher, Zvonko Vranesic, Safwat Zaky
By Prof R.R.Karwa

2. BASIC STRUCTURES OF COMPUTERS
Part A
BASIC STRUCTURES OF COMPUTERS

3. Computer Fast electronic machine Accepts digitized Input
Process stored instructions(Program)
Produce Output

4. Functional Units Figure 1.1. Basic functional units of a computer.
Arithmetic
Input
and
logic
Memory
Output
Control
I/O
Processor
Figure Basic functional units of a computer.

5. (ALU + Control Unit = CPU)
Functional Unit
Input Unit : Accepts data from I/p devices, convert that data into computer acceptable format and supplies converted data to computer system for further processing.
Output Unit : Accepts result produced by computer which is in computer acceptable format, convert that into human readable format and lastly supplied converted result to outside world through o/p devices.
ALU : Place where actual execution takes place during processing.
Control Unit : Direct all activities in computer.
(ALU + Control Unit = CPU)

6. Functional Unit
Memory Unit: Stores a) data to be processed b) intermediate result of processing c) Final result before result are released to o/p device
Two classes of Storage (Memory) :
i)Primary (Internal/Main memory) : directly accessed by CPU, Fast, Volatile (Content erased when power interrupt), Non- removable, Example: RAM & Cache
ii)Secondary (External memory/Auxiliary memory): Non volatile, removable, Larger & Cheaper, Example: Hard drive, optical disk, magnetic disk etc.

7. Cache Memory
Volatile computer memory that provide high speed data access to processor
Stores frequently used computer data.
At start, Cache is empty. All data is in Main memory. As during execution data is required, it is fetched from main memory and copies placed in cache.
Fetching from Cache reduces processing time.
Example: (in classroom)

8. Computer Organization Vs. Computer Architecture
Architecture: refers to those attributes of system that is visible to programmer, that have a direct impact on Logical execution of a program. Architecture attributes include Instruction set, Number of bits used to represent data type, techniques for addressing memory etc.
Organization: refers to operational unit and their interconnections that realize the architectural specification. Organizational attribute includes H/w details transparent to programmer such as Control signals, interfaces between computer and peripherals etc.
(Creating a design of house is Architecture while Building the house is Organization)

9. Historical Perspective : Generations of Computers
First ( , Processing using Vaccum tube, faster than earlier mechanical & electromechanical technology, assembly language was used to prepare program and was translated into machine language for execution)
Second ( , Transistor invented & replaced vaccum tube, faster than first generation, high level language developed & used, compilers developed to convert high level to assembly which was then translated into machine language, separate I/O processors developed that improved performance, Manufacturer Example : IBM)
Third ( , Many transistor on single chip that is Integrated Circuits, Introduction of Microprogramming, Parallelism, Pipelining, Cache memory, Example: System 360 mainframe computer from IBM)

10. Historical Perspective : Generations of Computers
Fourth: (1975 onwards, Tens of thousand of Transistors on a single chip, named Very large scale IC. Complete processor on one chip : microprocessor, Organizational concept evolved, LAN WAN MAN introduced, Manufacturer example: Texas, Intel, Motorola etc. )
Beyond The Fourth : (Computer featuring Artificial Intelligence, Parallel machines, Distributed system are examples of current trends.)

11. BUS Structures
There are many ways to connect different parts inside a computer together.
A group of lines that serves as a connecting path for several devices is called a bus.
Lines carry data, address. In addition, BUS must have Lines for control purposes

12. BUS Structures Single bus: Low cost, Flexible
Multiple bus: Achieve more concurrency by allowing 2 or more transfer at a same time that lease better performance but at increased cost.

13. Performance of Computer
Measured by How quickly it can execute program
Factors/Affected by:
a) Compiler
(High level to machine language)
b) Cache Memory (Slide 6)
c) Technology = VLSI (Slide 9)
d) Processor & System Organization (Next slide)
== Parallelism, Pipelining, Multicore processor, Multicomputer, Multitasking
e) Instruction set CISC & RISC (Later units)

14. Performance of Computer: Processor & System Organization
Parallelism: Execute instruction concurrently. For example, next instruction could be fetched from memory at same time that an arithmetic operation is being performed on register operands of instruction (Pipelining)
Multicore processors: Multiple processors on a single chip, called as Core. (Dual core, Quad core, Octal core)
Multiprocessors: Large computer system may contain number of processor units, termed as Multiprocessors.
Execute a number of different application tasks in parallel Execute subtasks of a single large task in parallel

15. Performance of Computer: Processor & System Organization
Multicomputer : Interconnected group of complete computers to achieve high computational powers.
Multitasking : Performing multiple task over a certain period of time by executing them concurrently. Computer resource can be used efficiently.

16. Part B
MACHINE INSTRUCTIONS

17. Memory Location and Addresses
second word
first word
Figure Memory words. n
bits
last word i
th word •
Memory consists of many millions of storage cells, each of which can store 1 bit.
Data is usually accessed in n-bit groups. n is called word length.
Accessing main memory to store or retrieve a single item of information requires address for each item.
A k-bit address memory has 2k memory locations, namely 0 – 2k-1, called memory space.

18. Memory Location and Addresses
32-bit word length example
32 bits • b b b b 31 30 1
Sign bit: b =
for positive numbers 31 b = 1
for negative numbers 31
(a) A signed integer
8 bits
8 bits
8 bits
8 bits
ASCII
ASCII
ASCII
ASCII
character
character
character
character
(b) Four characters

19. Byte and Word Addressing Memory
It is impractical to assign distinct addresses to individual bit locations in the memory.
The most practical assignment is to have successive addresses refer to successive byte locations in the memory – byte-addressable memory.
Byte locations have addresses 0, 1, 2, … If word length is 32 bits, they successive words are located at addresses 0, 4, 8,…
Byte is smallest addressable unit for a CPU. Such computers are called Byte Addressable.

20. Byte and Word Addressing Memory: Big Endian & Little Endian
Big Endian: Bytes are numbered starting with MSB of a word. Word is given the same address as its MSB. Little Endian: Bytes are numbered starting with LSB of a word. Word is given the same address as its LSB.

21. Byte and Word Addressing Memory: Big Endian & Little Endian
Byte address
Byte address 1 2 3 3 2 1 4 4 5 6 7 4 7 6 5 4 • • k k k k k k k k k k 2 - 4 2 - 4 2 - 3 2 - 2 2 - 1 2 - 4 2 - 1 2 - 2 2 - 3 2 - 4
(a) Big-endian assignment
(b) Little-endian assignment
Figure Byte and word addressing.

22. Memory Operations Load (Read/Fetch) Store (Write)
Transfer data from Memory location to CPU.
2 Steps
CPU sends the address of desired location to the main memory & request to read its content.
Main memory reads the data stored at that address & sends them to CPU.
Store (Write)
Transfer data from CPU to Specific Memory location, destroying former contents of that location.
CPU sends the address of desired location to the main memory, together with the data to be written to that location.

23. Instruction & Instruction Sequencing
Task carried out by Computer program consist of sequence of small steps.
4 Types of Operation:
Data transfer between memory & register (MOV,PUSH,POP)
Arithmetic & Logic Operations on Data (ADD,SUB,MUL,DIV)
Program sequencing & control (LOOP)
I/O Transfers (IN,OUT)

24. Instruction & Instruction Sequencing
Register Transfer Notation (RTN)
Identify a location by a symbolic name standing for its hardware binary address (LOC, R0,…)
Contents of a location are denoted by placing square brackets around the name of the location (R3 ←[R1]+[R2])
Assembly Language Notation
Represent machine instructions and programs.
Move LOC, R R1←[LOC]
Add R1, R2, R R3 ←[R1]+[R2]

25. Basic Instruction Types/Formats
Three address
Format: Operation Source1, Source2, Destination
ADD A,B,C C <- [A] + [B]
Two address
Format: Operation Source, Destination
ADD A,B B <- [A] + [B]
(Problem: Original content of B is destroyed.
Solution: MOV A,R0
ADD B,R0
MOV RO,C i.e C <- [A] + [B]

26. Basic Instruction Types/Formats
One address
Format: Operation Source/Destination
ADD A AC <- AC + [A]
Example: C <- [A] + [B] i.e. LOAD A (AC <- A)
ADD B (AC <- [B] + AC)
STORE C (C <- AC)
Zero address
Format: Operation ( NO Source/Destination)
Example: PUSH

27. Numerical Example: Evaluate (A+B)  (C+D) Three-Address
ADD A, B, R1 ; R1 ← M[A] + M[B]
ADD C, D, R2 ; R2 ← M[C] + M[D]
MUL R1,R2,X ; M[X] ← R1  R2

28. Example: Evaluate (A+B)  (C+D) Two-Address
MOV A,R1 ; R1 ← M[A]
ADD B,R1 ; R1 ← R1 + M[B]
MOV C,R2 ; R2 ← M[C]
ADD D,R2 ; R2 ← R2 + M[D]
MUL R1, R2 ; R2 ← R1  R2
MOV R2,X ; M[X] ← R2

29. Example: Evaluate (A+B)  (C+D) One-Address
LOAD A ; AC ← M[A]
ADD B ; AC ← AC + M[B]
STORE T ; M[T] ← AC
LOAD C ; AC ← M[C]
ADD D ; AC ← AC + M[D]
MUL T ; AC ← AC  M[T]
STORE X ; M[X] ← AC

30. Example: Evaluate (A+B)  (C+D) Zero-Address
PUSH A ; TOS ← A
PUSH B ; TOS ← B
ADD ; TOS ← (A + B)
PUSH C ; TOS ← C
PUSH D ; TOS ← D
ADD ; TOS ← (C + D)
MUL ; TOS ← (C+D)(A+B)
POP X ; M[X] ← TOS

31. Instruction Execution and Straight-Line Sequencing
Address
Contents
Assumptions:
- One memory operand
per instruction
- 32-bit word length
- Memory is byte
addressable
- Full memory address
can be directly specified
in a single-word instruction
Begin execution here i
Move
A,R0
3-instruction i
+ 4
Add
B,R0
program
segment i
+ 8
Move
R0,C A
Data for B
the program
Two-phase procedure
Instruction fetch
Instruction execute C
. A program for C ¬ [A] + [B].

32. Instruction Execution and Straight-Line Sequencing
CPU contains register PC that holds the address of instruction to be executed next. To begin execution, address of first instruction must be placed in PC.
CPU control circuits use the information in PC to fetch & execute the instruction in increasing order, referred as Straight line sequencing.
As each instruction is executed, the PC is incremented by 4 to point next instruction

33. Instruction Execution and Straight-Line Sequencing
Two-phase procedure
Instruction fetch
Instruction is fetched from memory location whose address is in the PC & is placed in Instruction register
Instruction execute
Instruction is in the IR is examined to determine which operation is to be performed. Operation is performed by processor. Between this two phase, PC is advanced to next instruction. After first execution phase is over, New instruction fetch can begin

34. ADDRESSING MODES