VLSI Synthesis and Simulation Tools Nitin Yogi 01/09/2009

VLSI Synthesis and Simulation Tools Nitin Yogi 01/09/2009
ELEC / Spring 09 Low Power Design of Electronic Circuits VLSI Synthesis and Simulation Tools Nitin Yogi 01/09/2009 Spring 09, Jan 9 ELEC5270/6270 Lecture 2

X-Win32 X-Win32 is used to log into UNIX session
Use Windows Auburn login and password to log into X-Win32 session. Spring 09, Jan 9 ELEC5270/6270 Lecture 2

Start X-Win32 from here Spring 09, Jan 9 ELEC5270/6270 Lecture 2

Windows Security Alert Warning
If Windows Security Alert window pops up, press OK Spring 09, Jan 9 ELEC5270/6270 Lecture 2

X-Win32 Login Screen Spring 09, Jan 9 ELEC5270/6270 Lecture 2

Sometimes X-Win32 may hang at this screen
Right-click on the X-Win32 icon in the task-bar and click X-Config Spring 09, Jan 9 ELEC5270/6270 Lecture 2

When X-Win32 doesn’t load …
Click on Engineering and then click on Remove. Then restart X-Win32 Spring 09, Jan 9 ELEC5270/6270 Lecture 2

You might also get this screen
Double click on “Scan for Unix/Linux hosts” Click on any of the server names and click on “Select” Spring 09, Jan 9 ELEC5270/6270 Lecture 2

You might also get this screen
Click “OK” Spring 09, Jan 9 ELEC5270/6270 Lecture 2

Command prompt to type commands in
UNIX session Setup the softwares required to run the tools for simulation, synthesis and test At the command prompt type the following command and hit “Enter” >> user-setup Command prompt to type commands in Spring 09, Jan 9 ELEC5270/6270 Lecture 2

User Setup screen Click on button “Electronics Data Analysis (EDA)”
Spring 09, Jan 9 ELEC5270/6270 Lecture 2

User Setup screen 3. Click the X button on the top right
2. Click on the following software packages: eda/Modelsim/6.4 eda/ICFlow/2007.2 eda/DFT/2007.3 1. Go to the bottom of the option screen ELEC5270/6270 Lecture 2 Spring 09, Jan 9

Click on “Save and Quit”

The Added modules will be displayed here
Press “Commit Changes” Spring 09, Jan 9 ELEC5270/6270 Lecture 2

X-Win32 reset Exit X-Win32 and restart the X-Win32 session again as described earlier Spring 09, Jan 9 ELEC5270/6270 Lecture 2

UNIX environment When you log-in into X-Win32, the current default directory is the H: of windows system Some useful UNIX commands >> cd <directory_name>: change directory >> cd .. : go up one directory >> ls: list contents of directory >> pwd: display the full path of the current dir. >> mkdir: create directory Spring 09, Jan 9 ELEC5270/6270 Lecture 2

Designing, compiling and simulating designs
In the current design directory (where your HDL file resides) run the following commands: >> vlib work >> vmap work work To simulate any design, you need to compile your design first. Compile your VHDL design using the command: >> vcom <VHDL filename> e.g. >> vcom my_ckt.vhd ModelSim tool is used for simulating the design To invoke ModelSim, use the following command: >> vsim <design_name> e.g. >> vsim my_ckt Note vsim command takes the design name as the input and not the HDL file Spring 09, Jan 9 ELEC5270/6270 Lecture 2

1. Click on “View > List” to select it (displayed as a tick)
2. Click on “View > Objects” to select it (displayed as a tick) Spring 09, Jan 9 ELEC5270/6270 Lecture 2

Right click the input signal name and then click Force

Enter the value of the signal over here and then click OK

To simulate, click Simulate > Run > Run 100

Useful resource “VHDL Design and Simulation using ModelSim” on Prof. Nelson’s website Spring 09, Jan 9 ELEC5270/6270 Lecture 2

Spring 09, Jan 9 ELEC5270/6270 Lecture 2 *From Prof. Nelson’s slides

Synthesis We shall use the tool Leonardo to synthesize the behavioral description into structural level netlist Command to invoke Leonardo is: >> leonardo & Spring 09, Jan 9 ELEC5270/6270 Lecture 2

Click on LeonardoSpectrum Level 3 and then click OK

Click on Advanced FlowTabs

Select the library and then click on “Load Library”

Select your HDL file by clicking “Open files”

Current selected designs will be displayed in this list
Click on the “Read” button to read the current selected HDL design(s) into the tool Spring 09, Jan 9 ELEC5270/6270 Lecture 2

Area or Delay optimization of circuit can be selected from here
Click “Optimize” to synthesize the circuit Spring 09, Jan 9 ELEC5270/6270 Lecture 2

“Report Area” gives the types and number of gates used

“Report Delay” gives the critical path and its delay

Enter a name for the output file and select the format.
Click “Write” to write the synthesized design to file Spring 09, Jan 9 ELEC5270/6270 Lecture 2

Preparing for simulation of synthesized netlist (Verilog format)
Compile the gate designs that will be used by your Verilog synthesized netlist The gate designs are in a file named “adk.vhd” at the location $ADK/technology Type the following command in your current working directory : >> vcom $ADK/technology/adk.vhd -work ./work/ Compile Verilog netlist >> vlog <Verilog file_name> e.g. >> vlog my_ckt.v Simulate Verilog design using ModelSim >> vsim <design_name> e.g. >> vsim my_ckt Spring 09, Jan 9 ELEC5270/6270 Lecture 2

Commands for Analogue Simulation
Analogue simulation set-up commands > ana > setenv MGC_IC_GENERIC_LIB /opt/mentor/ICFlow/2007.2/mgc_icstd_lib/generic_lib/ > setenv ADK_TECH tsmc018 > setenv MGC_AMS_HOME /opt/mentor/anacad/ > unlimit Design architect invocation command > da_ic & Spring 09, Jan 9 ELEC5270/6270 Lecture 2

Import Verilog Netlist
File > Import Verilog Spring 09, Jan 9 ELEC5270/6270 Lecture 2

Import Verilog netlist (cont.)

To open imported netlist click on “Schematic”

Click on “Simulation” to enter simulation mode

Setup analogue simulation environment
Click on Lib/Tmp/Inc > Libraries Spring 09, Jan 9 ELEC5270/6270 Lecture 2

Setup analogue simulation environment (Libraries)

Power Supply (VDD) specification file

Setup analogue simulation environment (Analyses)
Click on Analyses Spring 09, Jan 9 ELEC5270/6270 Lecture 2

Setup analogue simulation environment (Analyses)
Click on Transient > Setup Spring 09, Jan 9 ELEC5270/6270 Lecture 2

Setup analogue simulation environment (Forcing signals)
Click on the signal and then click on Forces > Add Spring 09, Jan 9 ELEC5270/6270 Lecture 2

Setup analogue simulation environment (Forcing signals)

Files generated by DA_IC*
Spring 09, Jan 9 ELEC5270/6270 Lecture 2 *From Prof. Nelson’s slides

Working directory of DA_IC

Force file generated by DA_IC

Setup analogue simulation environment (Measurements)
Click on Measurements > Define Spring 09, Jan 9 ELEC5270/6270 Lecture 2

Click on Measurements > Edit Spring 09, Jan 9 ELEC5270/6270 Lecture 2

Click on “Netlist” and then “Run ELDO”
Run Simulation Click on “Netlist” and then “Run ELDO” Spring 09, Jan 9 ELEC5270/6270 Lecture 2

Wave Viewer (EZWAVE) Invoke EZWAVE using the command >> ezwave
Note: Ensure the UNIX commands to set-up the analogue simulation environment (e.g. ana, setenv … etc. ) are executed before invoking ezwave Spring 09, Jan 9 ELEC5270/6270 Lecture 2

EZWAVE window Click on Open button to open a waveform database file (*.wdb) Spring 09, Jan 9 ELEC5270/6270 Lecture 2

Probed Signals will be loaded here
Probed Signals will be loaded here. Drag and drop the required signals in the right-hand side waveform window. Spring 09, Jan 9 ELEC5270/6270 Lecture 2

VLSI Synthesis and Simulation Tools Nitin Yogi 01/09/2009

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VLSI Synthesis and Simulation Tools Nitin Yogi 01/09/2009

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