1. ECE 171 Digital Circuits Chapter 10 Programmable Logic Devices (PLD)
Herbert G. Mayer, PSU
Status 5/3/2016
Copied with Permission from prof. Mark PSU ECE

2. Syllabus Taxonomy of ICs PLDs Fuses PLD Implementation PROMs PLAs PALs
GALs
References

3. Taxonomy of ICs Design Methodology SML (S small, M medium, L large)
Standard Components (SSI/MSI/LSI)
Off-the-shelf Components
Basic Universal Building Blocks (AND, OR, NAND, NOR…)
Application-Specific Standard Parts (ASSP)
Target Specific Application Area, but not Customer
e.g. Printer Controller, USB Interface IC, HDD I/F
Application-Specific IC (ASIC)
Custom Design of IC Targeting Specific Market
Full-custom, standard cell, gate-arrays
e.g. ATI 3D Graphics Engine
Programmable Logic Devices (PLD)
Can be used to implement wide variety designs
e.g. FPGA (Field-Programmable Gate Arrays)

4. PLDs
Programmable logic device (PLD) is an electronic component to build reconfigurable circuits
Unlike a logic gate with fixed function, a PLD has no function specified at the time of manufacture
Before a PLD can be used, it must be programmed
Programming a PLD means customizing for specific purpose
Also called configuring the PLD, or reconfiguring
Configuring consists of “blowing” certain fuses, thus enabling (or disabling) some functions
Often the initial functions included all options, such as a signal and ALSO its complement, which would not be meaningful!
One of the 2 must be eliminated to create a working device

5. PLDs
The abstract PLD below has 2 inputs, both of which and their complements are connected to and gates and thus to outut!
All have a via (path) over fuses that can (and some must) be blown to leave only meaningful functions

6. Reason for PLDs Shortened design time Rapid design changes
Rapid prototyping!
Rapid design changes
Reprogrammable
No masks, jumpers, PCB traces
Decreased PCB real estate, i.e. silicon space on IC
Less space than multiple standard logic packages
Improved reliability
Fewer packages, fewer external interconnects

7. Types of PLDs Programmable Logic Devices (PLDs)
PROM: Programmable Read Only Memory (1960s)
PLA: Programmable Logic Array [Signetics] (1975)
PAL:TM Programmable Array Logic [MMI] (1978)
GAL:TM Generic Array Logic
CPLD: Complex PLD
FPGA: Field Programmable Gate Array
PALÔ and GALÔ are registered trademarks of Lattice Logic

8. AND/OR Array Architecture
Device type AND array OR array Product term sharing
PROM Fixed at factory Programmable Yes
PLA Programmable Programmable Yes
PAL/GAL Programmable Fixed at factory No

9. Programmable Symbology

10. “Fuses”
“Fuses” were actual (real) fuses in early technology, now they aren’t always fuses --just called fuses:
Can be: fuses, transistor circuits, or SRAM-based
Volatile and nonvolatile
Nonvolatile
UV (ultra-violet erasable)
EE (electrically erasable)
Universal Programming Unit (from manufacturer)
Fuse map
JEDEC standard format (Joint Electronics Device Engineering Council)
Several programs generate (MACHXL, ABEL, CUPL)

11. PLD Implementation PROM PLA Schematic PAL/GAL Capture CPLDs Design
Tools
Fuse
Map
HDL
Universal
Programmer
Tool and PLD vendors: Xilinx, Altera, Lattice

12. PROMs
How many minterms? Generating all of them, then select among them,
What’s the impact of adding another input? Doubling AND array!
MaskROM – fully programmed one time at the factory. Game cards.

13. PAL vs. PLA
PLAs and PALs are both programmable logic devices that implement combinational circuits
A PLA has a programmable and-gate array, and a programmable or-gate array
A PAL has a programmable and-gate array, and a fixed or-gate array (newer, yet more restricted)
As a result, PLAs are slower (longer path), harder to implement, and more expensive (more silicon real-estate)
Detail on both below . . .
Obsolete but show the evolution of PLDs – desire to have programmable AND plane

14. PLAs
Programmable logic arrays (PLA) are PLD used to implement a specific combinational circuits
PLA consists of and-gate planes with 2n and-gates for n inputs
Linked to or-gate planes producing output signals
There are m outputs
Allows generation of sums of products of input signals
PLAs differ from PALs by allowing both and- and or-gate planes to be programmable!
Obsolete but show the evolution of PLDs – desire to have programmable AND plane

15. Generic PLAs
Obsolete but show the evolution of PLDs – desire to have programmable AND plane

16. PLA
Obsolete but show the evolution of PLDs – desire to have programmable AND plane

17. PALs
Programmable arrays logic (PAL) is a technology used to implement logic functions
Introduced 1978 by Monolithics Memories Inc. (MMI); now Lattice semiconductors in Oregon
MMI trademarked the term “PAL”
PALs consist of small PROMs plus added output logic to implement any desired logic function
Using specialized machines, PAL devices were field-programmable, i.e. in the end-customer lab
Obsolete but show the evolution of PLDs – desire to have programmable AND plane

18. PALs PALs come in several variants:
One-time programmable (OTP) devices could not be updated after initial programming
MMI offered a similar family called HAL, or "hard array logic", which were like PAL devices mask-programmed at factory
UV erasable versions had a quartz window over the chip die and could be erased for re-use with an ultraviolet light source; like EPROMs
Later versions (e.g.: PALCE22V10) were flash erasable devices

19. PALs
Flash Erasable: type of non-volatile storage device (similar to EE Prom) where erasing must be done by block
Not by individual datum
Superseded in late 1990 by FEPROMs that could be re-written, some fixed but large number of times

20. PALs/GALs
This example shows a PAL that doesn’t permit product term sharing

21. PAL with function sharing or additional inputs

22. Advantages to PLDs Shorten design time Rapid design changes
Rapid prototyping!
Rapid design changes
Reprogrammable
No masks, jumpers, PCB traces
Decrease PCB “real estate”
Less space than multiple standard logic packages
Improve reliability
Fewer packages, fewer external interconnects

23. PALxxyyzz Nomenclature
xx Maximum number of AND array inputs
zz Maximum number of dedicated outputs
y Type of outputs
Combinational
H active high
L active low
P programmable
C complementary
Registered
R registered
RP registered, with programmable polarity
Versatile
V programmable as combinational or registered

24. Nomenclature Examples
PAL3H2
3 inputs
2 outputs
Active H outputs
PAL16L8
16 inputs
8 outputs
Active L (0s of function)
PAL22V10
22 inputs
10 outputs
Active L or H (1s or 0s)
Registered if desired

25. PAL

26. GAL
Emulate any PAL
Reprogrammable
Fuses are non-volatile memory cells

27. CPLDs – Complex PLDs

28. Designing with PROMs A B C F 0 0 0 0 0 0 1 0 0 1 0 1 0 1 1 0 1 0 0 0
Address Data
XXXXXXX
XXXXXXX
XXXXXXX
XXXXXXX
XXXXXXX
XXXXXXX
XXXXXXX
XXXXXXX F C B A
Additional functions/outputs – wider bit word

29. Example Implement: F1 = inverter of A (NOT A) F2 = OR gate
F3 = NAND gate
F4 = XOR gate
With:
a PROM
a PLA
a PAL
A B F1 F2 F3 F4

30. PROM Implementation NOT, OR, NAND, XOR A B F1 F2 F3 F4 0 0 1 0 1 0
Address Data A F
Fuse map

31. PLA Implementation NOT, OR, NAND, XOR A B F1 F2 F3 F4 0 0 1 0 1 0
What would have happened if we’d chosen a different covering for the K-map for F3? Same number of terms…
Unable to share since the B’ term isn’t used anywhere else

32. PLA Implementation NOT, OR, NAND, XOR A B F1 F2 F3 F4 0 0 1 0 1 0
What are the shared product terms? Highlight in red

33. PAL Implementation NOT, OR, NAND, XOR A B F1 F2 F3 F4 0 0 1 0 1 0

34. Logic Conventions Positive Logic Convention (PLC)
Signals always “active high” (“asserted high”)
Bubble or negation indicator to show complementation
Direct Polarity Indication (DPI)
“mixed logic” notation
Suffix (H) or (L) indicates active high H or active low L
Polarity indicator or wedge to indicate active low L
PLC DPI Type of
Signal Name Signal Name Signal
A or A(H) A(H) or A(L) Active High
B or B(H) B(H) or B(L) Active Low

35. Indicator Matching

36. Detailed DPI Example
This is correct only if we assume the input names given

38. Databook Examples
Three-state bus buffer (buffer/driver). High impedance or “Z” – will be discussed later
G is active low enable. A/F are active H.
BCD to 7-segment display decoder with blanking control
Blanking input (BI) will be discussed in detailed example shortly
Open-collector outputs likewise (diamonds)
Symbol uses DPI with positive logic with signal matching (all active high except BI which has overbar and wedge)
Could have used A(H)…D(H) and a(H)…g(H) and BI(L) -- no overbar!
DMUX
DMUX is decoder with an enable input.
Note G2A and G2B are active low while G1 is active H
Outputs are active L (unlike text!) and are note signal name matched
REFER TO DATA SHEET IN CLASS!!!

39. Bibliography
PLD:
PLA:
PAL: