1. Development of SEU-robust, radiation-tolerant and industry-compatible programmable logic components
Sandro Bonacini
CERN

2. Outline Motivation and objectives TID hardening SEU hardening
Experimental results for SEU-robust structures
PLD design description
FPGA design description
Sandro BONACINI

3. Motivation
High-Energy Physics would benefit from the availability of radiation-hard programmable logic
FPGAs
Fast design development
Flexibility (changing requirements, failure recovery, …)
PLDs
Glue logic, simple state machines
Hard fixes in the late stages of a project
Commercial devices do not attain LHC radiation levels
>30 Mrad total dose
SEUs from intense flux of hadrons
~1015 hadrons/cm2 in 10 years LHC
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4. Objectives Programmable logic components FPGA PLD
TID-tolerant to experiment upgrades inner tracker levels
Built-in SEU hardness
Configuration bank and user registers…
…protected at circuit level against SEUs
User can avoid utilization of SEU hardening techniques at HDL level and/or reconfiguration techniques for program restoration
FPGA
compatible with an existing device, ~25k gates, 256 I/Os
in 0.13μm CMOS
PLD
compatible with 16LV8 device, 10 inputs, 8 bidirectional
in 0.25μm CMOS
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5. Total Ionizing Dose hardening
Design practices for TID hardening
0.25μm CMOS technology
Enclosed Layout Transistors
Guard-rings
0.13μm CMOS technology
Sufficiently TID-hard for digital logic without ELT
Faccio and Cervelli, “Radiation-induced edge effects in deep submicron CMOS transistors”, IEEE Transactions on Nuclear Science, vol. 52, December 2005
Use of linear transistors with W>0.30μm
O.25 micron
O.13 micron
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6. Single-Event Upset hardening
Circuit level SEU protection
SEU-robust register
used for configuration storage
…and user data
Based on Dual-Interlocked Cell (DICE)
Protection against Single-Event Transients (SETs)
Which occur in combinatorial logic
Duplication
SEU-R FF
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7. Dual-Interlocked Cell (DICE)
4 memory nodes
Each memory node is correlated to 2 other memory nodes
Interlock
Symmetric cell
Each node is equivalent to the others
2 stable states
(1,0,1,0)
(0,1,0,1)
pMOS propagate right only low values
nMOS propagate left only high values - 1 1 1z 1 0z A B C D
Intrinsically immune to single-node particle hits
Vulnerable to multiple-node particle hits
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8. …add clock driven transmission gates to access memory nodes…
SEU-robust latch
…add clock driven transmission gates to access memory nodes… A B C D Q0 Q1
ck0
ck1
ck0n
ck1n D0 D1 A B C D
Fully 2× redundant
2 inputs
2 outputs
2 clock buffers
Normally they have the same logic levels
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9. Register layout for SEU robustness
SEU-register is composed by a master latch and a slave latch
Master nodes: MA, MB, MC, MD
Slave nodes: SA, SB, SC, SD
Latch is vulnerable to multiple-node particle hits on correlated nodes
The nodes of the two latches are interleaved in order to increase the distance between correlated nodes
Less probability of multiple-node particle hit
ck0
ck1
ck0n
ck1n D0 D1 MA MB MC MD Q0 Q1 SA SB SC SD SA
&
output
buffer
clock MB SB MA SC MD SD MC
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10. SET protection: duplicated logic
Protection against Single-Event Transients (SETs)
Which occur in combinatorial logic and propagate to the flip-flops
Non SET-robust FF
Combinatorial
Logic
SET-robust
Duplicate combinatorial logic
Use SEU-robust FF
SEU-robust FF has 2 inputs and 2 outputs
Can tolerate an SEU on one of the two inputs.
Duplicate data path alleviates the problem of latching erroneous states
SEU-R FF
Combinatorial
Logic
SEU-R FF
Combinatorial
Logic
SEU-R FF
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11. Heavy-ion beam tests on SEU-robust register
Two test chips were fabricated
0.25μm CMOS
2×2 mm2, 1024 SEU-robust registers
0.13μm CMOS
1×2 mm2, 9216 SEU-robust registers, 4096 standard library registers
Static shift-register test
Stream in configuration
Beam start/stop
Retrieve configuration & compare
Dynamic shift-register test
Continuous configuration load, retrieve & compare while configuration clock is running and beam is on
USB interface
Test controller
Device Under Test (back)
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12. Test chip in 0.25μm CMOS Heavy-ion beam testing
Strong SEU robustness of the register cell up to an LET of 79.6 cm2MeV/mg
no errors observed in either static and dynamic test modes
At an LET of 112 cm2MeV/mg and only in the dynamic test mode, the register cell showed SEU sensitivity, with SEU cross-section of 6.2· cm2/bit
LHC environment: up to 17 cm2MeV/mg
Huhtinen and Faccio, “Computational method to estimate Single Event Upset rates in an accelerator environment”, Nuclear Instruments and Methods in Physics Research A 450 (2000)
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13. Test chip in 0.13μm CMOS 0.13μm CMOS Good static mode robustness
no errors up to 45.8 cm2MeV/mg
In dynamic mode register shows sensitivity
strongly dependent on angle of incidence of the beam
Suitable as configuration register
Not suitable as user register
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14. Radiation-tolerant PLDMn M2 M1 M3 M4 M5 M6 M7 M8
Mn-3
Mn-2
Mn-1 A1 A2 … Ap Q1 Q2 Qp OL
CLK
Compatible with 16LV8 commercial device
Fuse based
Laser programmable
10 inputs, 8 programmable input/outputs
Configurable AND matrix generates minterms
Fixed OR matrix sums minterms
8 minterms per output
Outputs can be registered or not
Outputs are fed back to AND matrix for generation of more complex functions
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15. Fuses & PLD chip layout
Fuses consist in a 7×1 μm2 metal line (aluminum)
Laser programmable
2080 programming fuses
Occupy 70% of core area
Chip size is 2×2 mm2
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16. Radiation-tolerant FPGA
Typical FPGA architecture
Array of 32×32 Logic Blocks (LBs)
Configurable routing
SRAM based
Reprogrammable
256 I/Os
Compatible with an existing commercial device
Same design tools can be reused
Synthesis, Place & Route
Logic block
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17. Logic Block 4-input-1-output Look-Up Table (LUT) Carry
implements any boolean function of 4 variables
holds its truth table in 16 configuration registers
can also be used as a 16×1-bit RAM block
31 configuration bits per LB are present and are organized in a shift-register structure
COUT
Carry
chain D YQ
SEU-R FF
A[0]
4-input
LUT Y
A[1]
A[2]
A[3]
CIN
CLK
S/R
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18. Programmable interconnectionsLB
pair
A[0]
B[0]
CLK DA
SET
A[3]
B[3]
A[1]
B[1]
RES
A[2]
B[2] DB YB
YQB
YQA YA
YQBin
YBin
A2out
B2out
DBout
YAout
YQAout
Tout
Tin
YAin
YQAin
A1out
B1out
RESout
YBout
YQBout
B1in
RESin
A1in
B2in
DBin
A2in
vdd
local
long
clock
double
18 wires per direction
6 long lines
12 short-distance lines
8 direct neighbor connections
Connections implemented with
tristate buffers
transmission gates
multiplexers
256 configuration registers in total
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19. Conclusions
An SEU-robust register structure was designed and tested in two CMOS technologies
Results obtained in the 0.25 μm technology demonstrate good robustness of the circuit up to 79.6 cm2MeV/mg
The 0.13 μm circuit showed good robustness in the static tests but appeared to be sensitive in the dynamic tests
Additional work is necessary for the FPGA user register
Our approach demonstrated the feasibility of the SEU-tolerant radiation-hard PLD and FPGA
PLD chip was fabricated
The LB of the FPGA design was finalized, work is on going to complete the FPGA with interconnection infrastructure
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