1. Chapter 7: Physical Implementation
Digital Design
Chapter 7:
Physical Implementation
Slides to accompany the textbook Digital Design, First Edition,
by Frank Vahid, John Wiley and Sons Publishers, 2007.
Some changes by Mark Brehob
Copyright by Frank Vahid
Instructors of courses requiring Vahid's Digital Design textbook (published by John Wiley and Sons) have permission to modify and use these slides for customary course-related activities, subject to keeping this copyright notice in place and unmodified. These slides may be posted as unanimated pdf versions on publicly-accessible course websites.. PowerPoint source (or pdf with animations) may not be posted to publicly-accessible websites, but may be posted for students on internal protected sites or distributed directly to students by other electronic means. Instructors may make printouts of the slides available to students for a reasonable photocopying charge, without incurring royalties. Any other use requires explicit permission. Instructors may obtain PowerPoint source or obtain special use permissions from Wiley – see for information.

2. Introduction
A digital circuit design is just an idea, perhaps drawn on paper
We eventually need to implement the circuit on a physical device
How do we get from (a) to (b)? B
elt W a r n k p w s IC
(a) Digital circuit design
(b) Physical implementation

3. Manufactured IC Technologies
We can manufacture our own IC
Months of time and millions of dollars
(1) Full-custom or (2) semicustom
(1) Full-custom IC
We make a full custom layout
Using CAD tools
Layout describes the location and size of every transistor and wire
A fab (fabrication plant) builds IC for layout
Hard!
Fab setup costs ("non-recurring engineering", or NRE, costs) high
Error prone (several "respins")
Fairly uncommon
Reserved for special ICs that demand the very best performance or the very smallest size/power B
elt W a r n k p w
Custom
Layout s IC F ab mo n
ths

4. Full Custom inverter
Note: image on right, while an inverter, isn’t the same as what’s asked for on the left (AFAIK). Not ideal, but image that does follow from that is hard to see (color on black).
Images from
and

5. Take away – full custom Very expensive and slow Best performance
Requires folks who really know what they are doing and requires them to take time
EECS 312 final project is to build a fairly small device (e.g. 4-bit adder) with certain space and power bounds. This is a multi-week thing!
Fabrication will generally not have any short cuts.
So might take months to get this spun.
Best performance
Can tune the heck out of things and make stuff go really fast or use very little power.
Where do you think this sees use?

6. Gate array From Wikipedia:
A gate array circuit is a prefabricated silicon chip circuit with no particular function in which transistors, standard NAND or NOR logic gates, and other active devices are placed at regular predefined positions and manufactured on a wafer, usually called a master slice. Creation of a circuit with a specified function is accomplished by adding a final surface layer or layers of metal interconnects to the chips on the master slice late in the manufacturing process, joining these elements to allow the function of the chip to be customized as desired.
Gate array master slices are usually prefabricated and stockpiled in large quantities regardless of customer orders. The design and fabrication according to the individual customer specifications may be finished in a shorter time compared with standard cell or full custom design.

7. Manufactured IC Technologies – Gate Array ASIC
(2) Semi-custom IC
"Application-specific IC" (ASIC)
(a) Gate array or (b) standard cell
(2a) Gate array
Series of gates already laid out on chip
We just wire them together
Using CAD tools
Vs. full-custom
Cheaper and quicker to design
But worse performance, size, power
Was quite popular
Sees less use today AFAICT k B
elt W a r n p w s ( b ) ( a ) k p s ( c ) IC ( d ) w w
eeks (
just wi r
ing) F ab

8. Manufactured IC Technologies – Gate Array ASIC
(2a) Gate array
Example: Mapping a half-adder to a gate array
Half-adder equations:
s = a'b + ab'
co = ab a c o ab
a'b
ab' b s G a t
e a r r a y

9. Manufactured IC Technologies – Standard Cell ASIC
(2) Semicustom IC
"Application-specific IC" (ASIC)
(a) Gate array or (b) standard cell
(2b) Standard cell
Pre-laid-out "cells" exist in library, not on chip
Designer instantiates cells into pre-defined rows, and connects
Vs. gate array
Better performance/power/size
A bit harder to design
Vs. full custom
Not as good of circuit, but still far easier to design k
BeltWarn p w s ( b )
Cell library ( a ) k w IC ( d ) p
cell row s
cell row
cell row ( c )
1-3 months
(cells and wiring)
Fab

10. Manufactured IC Technologies – Standard Cell ASIC
(2b) Standard cell
Example: Mapping a half-adder to standard cells
co = ab
s = a'b + ab' a ab
a'b
ab' co b s
cell row
cell row
gate array s c o a b
a'b
ab' ab
Notice fewer gates and shorter wires for standard cells versus gate array,
but at cost of more design and manufacturing effort
cell row

11. Question:
What are the key differences between standard cells and gate array design?

12. Implementing Circuits Using NAND Gates Only (We’ve been doing this since GA1!)
Gate array may have NAND gates only
NAND is universal gate
Any circuit can be mapped to NANDs only
Convert AND/OR/NOT circuit to NAND-only circuit using mapping rules
After converting, remove double inversions a b x
F=x' I
nputs 1 O
utput F a b
F=ab (a )' a a b
F=a+b
F=(a'b')'=a''+b''=a+b
Double inversion

13. Implementing Circuits Using NOR Gates Only
Example: Half adder
double inversion ( c ) a b s a ( b ) a b s a s b ( a )

14. Implementing Circuits Using NOR Gates Only
Example: Seat belt warning light on a NOR-based gate array
Note: if using 2-input NOR gates, first convert AND/OR gates to 2-inputs k p w
was s ( b ) w k p s 1 3 2 4 5 ( d ) k p s w ( c ) 1 3 4 2 5 ( a )

15. Programmable IC Technology – FPGA
7.3
Programmable IC Technology – FPGA
Manufactured IC technologies require weeks to months to fabricate
And have large (hundred thousand to million dollar) initial costs
Programmable ICs are pre-manufactured
Can implement circuit today
Just download bits into device
Slower/bigger/more-power than manufactured ICs
But get it today, and no fabrication costs
Popular programmable IC – FPGA
"Field-programmable gate array"
Developed late 1980s
Though no "gate array" inside
Named when gate arrays were very popular in the 1980s
Programmable in seconds

16. FPGA Internals: Lookup Tables (LUTs)
Basic idea: Memory can implement combinational logic
e.g., 2-address memory can implement 2-input logic
1-bit wide memory – 1 function; 2-bits wide – 2 functions
Such memory in FPGA known as Lookup Table (LUT)
F = x'y'
+ xy ( d )
F = x'y' + xy
G = xy' x 1 y F G 4x
1 Mem. 4x
1 Mem. 1 2 3 rd a1 a0 D ( c ) 4x
2 Mem. 10 00 01 1 2 3 rd a1 a0 x y D1 D0 F G ( e ) x y F 1 rd 1 1
y=0
x=0
F=1 1 1 1 2 1 1 1 3 x a1 y a0 D F ( a ) ( b )

17. FPGA Internals: Lookup Tables (LUTs)
Example: Seat-belt warning light (again) k p s w
BeltWarn ( a ) ( b ) k 1 p s w
Programming
(seconds)
Fab
1-3 months ( c ) 8x
1 Mem. 1 D w I C 2 3 4 5 6 7 a2 a1 a0 k p s

18. FPGA Internals: Lookup Tables (LUTs)
Lookup tables become inefficient for more inputs
3 inputs  only 8 words
8 inputs  256 words; inputs  65,536 words!
FPGAs thus have numerous small (3, 4, 5, or even 6-input) LUTs
If circuit has more inputs, must partition circuit among LUTs
Example: Extended seat-belt warning light system:
Sub-circuits have only 3-inputs each 8x 1
Mem. D 2 3 4 5 6 7 a2 a1 a0 k p s
kps'
BeltWarn
Partition circuit into 3-input sub-circuits k p s t d x w
BeltWarn ( b )
3 inputs
1 output
x=kps'
w=x+t+d x d t ( c ) 8x 1
Mem. D w 2 3 4 5 6 7 a2 a1 a0
x+t+d k p w s t d ( a )
5-input circuit, but 3-input LUTs available
Map to 3-input LUTs

19. LUTs

20. FPGA Internals: Lookup Tables (LUTs)
LUT typically has 2 (or more) outputs, not just one
Example: Partitioning a circuit among 3-input 2-output lookup tables a 8x 2
Mem. 8x 2
Mem. b c 1
First column unused; second column implements AND F e d 1 t
Second column unused; first column implements AND/OR sub-circuit d F 1 1 e 2 2 ( a ) 3 3 a a2 a2 a 4 4 1 b a1 a1 b 2 t c a0 5 a0 5 c 3 1 6 6 2 d F 7 7 3 e D1 D0 D1 D0 ( b )
(Note: decomposed one 4-input AND input two smaller ANDs to enable partitioning into 3-input sub-circuits) ( c )

21. FPGA Internals: Lookup Tables (LUTs)
Example: Mapping a 2x4 decoder to 3-input 2-output LUTs
Sub-circuit has 2 inputs, 2 outputs i1 i0 d0 8x 2
Mem. 8x 2
Mem. 10 01 00 00 10 01 d1 1 1 2 2
Sub-circuit has 2 inputs, 2 outputs d2 3 3 a2 a2 4 4 a1 a1 d3 a0 5 a0 5 6 6 7 7 D1 D0 D1 D0 i1 i0 d0 d1 d2 d3 ( a ) ( b )

22. FPGA Internals: Switch Matrices
Previous slides had hardwired connections between LUTs
Instead, want to program the connections too
Use switch matrices (also known as programmable interconnect)
Simple mux-based version – each output can be set to any of the four inputs just by programming its 2-bit configuration memory ( b ) m0 o0 o1 i0 s0 d s1 i1 i2 i3 m1 m2 m3
2-bit
memory
Switch matrix 4x 1
mux
FPGA (partial) 8x 2
Mem. 8x 2
Mem. 00 00 1 00 1 00 2 00 2 00 P0 3 00 3 00 P6 P1 a2 a2 4 00 4 00 P2 a1 m0 m1 o0 o1 m2 m3
Switch
matrix a1 P7 a0 5 00 a0 5 00 P3 6 00 6 00 7 00 7 00 D1 D0 D1 D0 P8 P9 P4 P5 ( a )

23. FPGA Internals: Switch Matrices
Mapping a 2x4 decoder onto an FPGA with a switch matrix
These bits establish the desired connections ( b ) m0 o0 o1 i0 s0 d s1 i1 i2 i3 m1 m2 m3
Switch matrix 4x 1
mux
FPGA (partial) 8x 2
Mem. 8x 2
Mem. 10 10 00 1 01 1 00 2 00 2 10 3 00 3 01 d3 a2 a2 4 00 4 00 i1 a1 a1 10 11 o0 d2 a0 5 00 a0 5 00 i0 m0 o1 6 00 m1 6 00 m2 11 7 00 m3 7 00 D1 D0
Switch D1 D0
matrix d1 d0 i1 i0 ( a )

24. F=A*B+C
G=A*B*C*!D*E

25. F=A*B+C
G=A*B*C*!D*E

26. FPGA Internals: Configurable Logic Blocks (CLBs)
LUTs can only implement combinational logic
Need flip-flops to implement sequential logic
Add flip-flop to each LUT output
Configurable Logic Block (CLB)
LUT + flip-flops
Can program CLB outputs to come from flip-flops or from LUTs directly
FPGA
CLB
CLB 8x 2
Mem. 8x 2
Mem. 00 00 1 00 1 00 2 00 2 00 P0 3 00 3 00 P1 a2 a2 4 00 4 00 P2 a1 00 o0 a1 P3 a0 5 00 o1 a0 5 00 m0 00 6 00 m1 6 00 m2 7 00 m3 7 00
flip-flop
CLB output D1 D0
Switch D1 D0
matrix 2x 1
1-bit
CLB
output
configuration
memory P6 P7 P8 P9 P4 P5

27. FPGA Internals: Sequential Circuit Example using CLBsd
CLB
CLB 8x 2
Mem. 8x 2
Mem. 11 10 01 00 00 01 10 11 1 1 2 2 3 3 a b a2 a2 w x y z 4 00 4 00 a1 10 11 o0 a1 ( a ) a0 5 m0 o1 a0 5 6 m1 6 m2 7 m3 7
Left lookup table D1 D0
Switch D1 D0 a2 a1 a0 D1 D0
matrix a b
w=a'
x=b' 1 1 1 1 1 1 1 1 1 1 2 x1 2 x1 2 x1 2 x1 1 1 1 1 z y x w
below unused ( b ) d c ( c )

28. FPGA Internals: Overall Architecture
Consists of hundreds or thousands of CLBs and switch matrices (SMs) arranged in regular pattern on a chip
Represents channel with tens of wires
Connections for just one CLB shown, but all CLBs are obviously connected to channels
CLB
CLB
CLB SM SM
CLB
CLB
CLB SM SM
CLB
CLB
CLB

29. FPGA Internals: Programming an FPGA
All configuration memory bits are connected as one big shift register
Known as scan chain
Shift in "bit file" of desired circuit
FPGA
CLB
CLB
Pin 8x 2
Mem. 8x 2
Mem. 11 01
Pclk 1 10 1 00 2 01 2 11 3 01 3 10 a2 a2 4 00 4 00 a a1 10 o0 a1 b a0 5 00 m0 o1 a0 5 00 m1 11 ( a ) 6 00 6 00 m2 7 00 m3 7 00 D1 D0
Switch D1 D0
matrix 1 2 x1 1 2x 1 1 2 x1 1 2 x1 z y x w c d ( b )
Pin
Conceptual view of configuration bit scan chain
is that of a 40-bit shift register
Pclk a ( c )
Bit file contents for desired circuit:
This isn't wrong. Although the bits appear as "10" above, note that the scan chain passes through those bits from right to left – so "01" is correct here.

30. Other Technologies Off-the-shelf logic (SSI) IC
7.4
Other Technologies
Off-the-shelf logic (SSI) IC
Logic IC has a few gates, connected to IC's pins
Known as Small Scale Integration (SSI)
Popular logic IC series: 7400
Originally developed 1960s
Back then, each IC cost $1000
Today, costs just tens of cents V C C I 14 I 13 I 12 I 11 I 10 I 9 I 8 I C I 1 I 2 I 3 I 4 I 5 I 6 I 7
GND

31. 7400-Series Logic ICs

32. Using Logic ICs
Example: Seat belt warning light using off-the-shelf 7400 ICs
Option 1: Use one 74LS08 IC having 2-input AND gates, and one 74LS04 IC having inverters
(a) Desired circuit I 14 I 13 I 12 I 11 I 10 I 9 I 8 k
(c) Connect ICs to create desired circuit p w
74LS08 I C s n I 1 I 2 I 3 I 4 I 5 I 6 I 7 ( a ) w k p I 14 I 13 I 12 I 11 I 10 I 9 I 8
(b) Decompose into 2-input AND gates k p s w n ( b ) s
74LS04 I C I 1 I 2 I 3 I 4 I 5 I 6 I 7 ( c ) a a

33. Other Technologies Simple Programmable Logic Devices (SPLDs)1 I 2 I 3
Simple Programmable Logic Devices (SPLDs)
Developed 1970s (thus, pre-dates FPGAs)
Prefabricated IC with large AND-OR structure
Connections can be "programmed" to create custom circuit
Circuit shown can implement any 3-input function of up to 3 terms
e.g., F = abc + a'c' O1
PLD I C
programmable nodes

34. Programmable Nodes in an SPLD
Fuse based – "blown" fuse removes connection
Memory based – 1 creates connection O1
PLD I C 3 2 1
programmable nodes p r o g r
ammable node
Fuse based ( a ) F
use
"unbl o
wn" fuse
"bl o
wn" fuse
Memory based
mem
mem 1 ( b )

35. PLD Drawings and PLD Implementation Example
Common way of drawing PLD connections:
Uses one wire to represent all inputs of an AND
Uses "x" to represent connection
Crossing wires are not connected unless "x" is present I 1 I 2 I 3
wired AND I 3 * I 2' × × O1
PLD I C
Example: Seat belt warning light using SPLD w
PLD I C s p k
kps' k p s w B
elt W a r n × × × × ×
Two ways to generate a 0 term

36. PLD Extensions × Two-output PLD3 2 1 ( a )
PLD C O1 O2 b FF ×
programmable bit
clk
Two-output PLD
PLD with programmable registered outputs

37. More on PLDs
Originally (1970s) known as Programmable Logic Array – PLA
Had programmable AND and OR arrays
AMD created "Programmable Array Logic" – "PAL" (trademark)
Only AND array was programmable (fuse based)
Lattice Semiconductor Corp. created "Generic Array Logic – "GAL" (trademark)
Memory based
As IC capacities increased, companies put multiple PLD structures on one chip, interconnecting them
Become known as Complex PLDs (CPLD), and older PLDs became known as Simple PLDs (SPLD)
GENERALLY SPEAKING, difference of SPLDs vs. CPLDs vs. FPGAs:
SPLD: tens to hundreds of gates, and usually non-volatile (saves bits without power)
CPLD: thousands of gates, and usually non-volatile
FPGA: tens of thousands of gates and more, and usually volatile (but no reason why couldn't be non-volatile)

38. Technology Comparisons
7.5
Technology Comparisons
Full-custom
Standard cell (semicustom)
Gate array (semicustom)
FPGA
PLD
Quicker availability
Faster performance
Lower design cost
Higher density
Lower power
Larger chip capacity
Easier design
More optimized

39. Technology Comparisons
(1): Custom processor in full-custom IC
Highly optimized
PLD
FPGA G a t e r y S
tanda d c
ell F
ull -
cus om
(3)
(4)
(2)
(1)
Easier design M o
e optimized
Custom Processor P g
ammable p
essor
(2): Custom processor in FPGA
Parallelized circuit, slower IC technology but programmable
Processor varieties
(3): Programmable processor in standard cell IC
Program runs (mostly) sequentially on moderate-costing IC
(4): Programmable processor in FPGA
Not only can processor be programmed, but FPGA can be programmed to implement multiple processors/coprocessors
IC technologies

40. Key Trend in Implementation Technologies
Transistors per IC doubling every 18 months for past three decades
Known as "Moore's Law"
Tremendous implications – applications infeasible at one time due to outrageous processing requirements become feasible a few years later
Can Moore's Law continue – No?