1. COMP541 Transistors and all that… a brief overview
Montek Singh
Sep 18, 2017

2. Transistors as switches
At an abstract level, transistors are merely switches
3-ported voltage-controlled switch
n-type: conduct when control input is 1
p-type: conduct when control input is 0

3. Silicon as a semiconductor
Transistors are built from silicon
Pure Si itself does not conduct well
Impurities are added to make it conducting
As provides free electrons  n-type
B provides free “holes”  p-type
Figure 1.26 Silicon lattice and dopant atoms

4. MOS Transistors MOS = Metal-oxide semiconductor 3 terminals
gate: the voltage here controls whether current flows
source and drain: are what the current flows between
structurally, source and drain are the same
Figure 1.29 nMOS and pMOS transistors

5. nMOS Transistors Gate = 0 Gate = 1 OFF = disconnect ON= connect
no current flows between source & drain
Gate = 1
ON= connect
current can flow between source & drain
positive gate voltage draws in electrons to form a channel
Figure 1.30 nMOS transistor operation

6. nMOS and pMOS Transistors
pMOS: Just the opposite
Gate = 1  disconnect
Gate = 0  connect
Summary:

7. CMOS Topologies There is actually more to it than connect/disconnect
nMOS: pass good 0’s, but bad 1’s
so connect source to GND
pMOS: pass good 1’s, but bad 0’s
so connect source to VDD
Typically use them in complementary fashion:
nMOS network at bottom
pulls output value down to 0
pMOS network at top
pulls output value up to 1
only one of the two networks must conduct at a time!
or output is undefined (or smoke may be produced!)
if neither network conducts  output will be floating

8. CMOS Gate Recipe Use complementary networks of p- and n-transistors
called CMOS (“complementary metal-oxide semiconductor”)
at any time: either “pullup” active, or “pulldown” active
never both!
VDD
Gnd
Use p-type here
pullup: make this connection when some combination of inputs
is near 0 so that output = VDD
pulldown: make this connection when some combination of inputs
is near VDD so that output = 0 (Gnd)
Use n-type here

9. CMOS Inverter Vout Vin Vout Vin Valid “1” Valid “0” Invalid A Y
Only a narrow range of input voltages result in “invalid” output values. (This diagram is greatly exaggerated)
Valid “1”
Valid “0”
Invalid
Vin
Vout
“1”
“0”
Vin A Y
inverter

10. CMOS Complements A A conducts when A is high conducts when A is low
conducts when A is high and B is high: A.B A B
conducts when A is low or B is low: A+B = A.B
Series N connections:
Parallel P connections:
conducts when A is high or B is high: A+B A B
conducts when A is low and B is low: A.B = A+B
Parallel N connections:
Series P connections:

11. Inverter A P1 N1 Y ON
OFF 1

12. NAND A B P1 P2 N1 N2 Y ON
OFF 1

13. 3-Input NAND

14. NOR

15. 3-input NOR

16. 2-input AND Gate?

17. A More Complex CMOS Gate
Design a single gate that computes
Step 1. Determine pull-down network that sets output to ‘0’
(A OR B) AND C  Y=0
Step 2. Determine pull-up network by walking through pulldown hierarchy, and
replacing n-transistors with p-transistors
series composition with parallel composition
parallel composition with series composition
Step 3. Combine the pull-up and pull-down networks together C A B C A B C A B Y

18. A More Complex CMOS Gate
Single gate that computes
called “complex gate” because it is not one of the basic gates (NAND, NOR, NOT, etc.)
this one is actually called OR-AND-INVERT (OAI)
symbol: C A B Y

19. One More Exercise Lets construct a gate to compute:
F = A+BC = NOT(OR(A,AND(B,C)))
Step 1: Draw the pull-down network
Step 2: The complementary pull-up network
this one is called AND-OR-INVERT (AOI)
Vdd A B C F A B C

20. One More Exercise Lets construct a gate to compute: 1
F = A+BC = NOT(OR(A,AND(B,C)))
Step 1: Draw the pull-down network
Step 2: The complementary pull-up network
Step 3: Combine and Verify
Vdd A B C F A A B C F 1 B C 1

21. Transmission Gates Transmission gate is a switch: Symbol: En A B En A
nMOS pass 1’s poorly
pMOS pass 0’s poorly
Transmission gate is a better switch
passes both 0 and 1 well
When EN = 1, the switch is ON:
A is connected to B
When EN = 0, the switch is OFF:
A is not connected to B
Symbol: En A B En A B En

22. Transmission Gate En IMPORTANT: Transmission gates are not drivers A B
will NOT remove input noise to produce clean(er) output
simply connect A and B together
current could even flow backward!
use very carefully!
immediately follow it up with a normal CMOS gate A B En

23. Logic using Transmission Gates
Typically combine two (or more) transmission gates
Together form an actual logic gate whose output is always driven 0 or 1
Exactly one transmission gate drives the output; all remaining transmission gates float their outputs
Example: XOR
when C = 0, TG0 conducts
F = A
when C = 1, TG1 conducts
F = A’
therefore:
F = A xor C
TG0
TG1

24. Tristate buffer and tristate inverter
When enabled: sends input to output
When disabled: output is floating (‘Z’)
Implementation:
Tristate buffer using only a pass gate
If on: output  input
If off: output is floating
Tristate inverter
Top half and bottom half are not fully complementary
Either both conduct: output  NOT(input)
will act as a driver!
Or both off: output is floating

25. Power and Energy Consumption

26. Power Consumption Power = Energy consumed per unit time
Dynamic power consumption
Static power consumption

27. Dynamic Power Consumption
Energy consumed due to switching activity:
All wires and transistor gates have capacitance
Energy required to charge a capacitance, C, to VDD is CVDD2
Circuit running at frequency f: transistors switch (from 1 to 0 or vice versa) at that frequency
Capacitor is charged f/2 times per second
assume 50% chance switching from 0 to 1
additional energy drawn from battery  CVDD2
assume 50% chance switching from 1 to 0
no additional energy taken from battery  stored energy is discharged
Pdynamic = ½CVDD2f
C is the total capacitance of circuit (“capacitive load”)
VDD is the supply voltage
f is the switching frequency

28. Static Power Consumption
Power consumed when no gates are switching
Caused by the quiescent supply current, IDD (also called the leakage current)
Pstatic or Pleakage = IDDVDD
VDD is the supply voltage
IDD is the leakage current

29. Power Consumption Example
Estimate the power consumption of a wireless handheld computer
VDD = 1.2 V
C = 20 nF
f = 1 GHz
IDD = 20 mA
P = ½CVDD2f + IDDVDD
= ½(20 nF)(1.2 V)2(1 GHz) + (20 mA)(1.2 V)
= 14.4 W mW
= W