Design guidelines for EMC of electronic devices

Design guidelines for EMC of electronic devices

Summary Introduction Guidelines for signal integrity
Guidelines for power integrity Guidelines for reduced radiated emission Reduction of I/O noise Spread-spectrum frequency modulation January 18

Introduction EMC should be taken into account at early design stage…
K. Armstrong, Advanced PCB design and layout for EMC January 18

Introduction Why taking into account EMC for ICs ?
K. Armstrong, Advanced PCB design and layout for EMC 4

Introduction Power integrity (PI) Signal integrity (SI) ESD, EFT, EOS
Which problems? Know your enemy Power integrity (PI) Signal integrity (SI) ESD, EFT, EOS Conducted emission (CE) Integrated circuits / electronic applications Radiated immunity (RI) Radiated emission (RE) Remark: even these problems are different, they can have the same root cause. Soving one of these problem can help to solve other problems. Example: SI, PI, CE, REproblems can be related to a bad PCB design of power or ground plane design, return path of the current not ensured  SI and PI problems. As common mode current appears, an important radiated emission can be produced. Oter example where SI, PI, RE, CE and CI, RI can be related. The design of the power and ground plane of the application is not good and an antiresonance appears. The IC can excite these antiresonance and generate an important voltage flcutuation of Vdd  PI, SI and CE problem. As the power plane voltage fluctuates, the cavity forms by the power and ground plane can act as a parasitic antenna  RE problem. If a cnducted disturbance is applied on the power plane at the PCB antiresonance frequency, a large voltage fluctuation appear and disturb the circuit operation  CI problem. At this frequency, the power and ground plane acts as parasitic but efficient antenna, able to couple a radiated disturbance  RI problem. Conducted immunity (CI) January 18

Guidelines for signal integrity
Design guidelines for EMC Guidelines for signal integrity January 18

Signal integrity (SI) issue Zc ; Tp VG VL Criterion for SI issue: if Tr is the rising or falling time of a signal, SI issues due to the propagation of the EM wave along the transmission line arise if: Overshoot VL or VG Vdd VIH Undershoot Undetermined level VIL Ringing t Longer setting time January 18

Signal integrity (SI) issue K. Armstrong, Advanced PCB design and layout for EMC January 18

Ensuring Signal integrity – Rule 1 Cancel reflection coefficient at each line terminals by impedance matching Impedance matching of a uniform transmission line with constant characteristic impedance Zc. Practical designs for a digital transmission: Zc Rpd Ct Vcc Rs : serial resistor= Rdriver - Zc Zc Rs Rpd Rpd : pull down resistor = Zc January 18

Ensuring Signal integrity – Rule 2 Control the characteristic impedance of transmission line (PCB track, package) and avoid line discontinuities Microstrip line configuration: W I εr t h Ideal ground plane January 18

Ensuring Signal integrity – Rule 2 Example: consider the following PCB stack-up. A digital link between 100 Ω driver and receiver is ensured by a microstrip line routed in layer 4. Propose a value for the line width. January 18

Ensure a controlled and short return current path.
Guidelines for signal integrity Ensuring Signal integrity – Rule 3 Ensure a controlled and short return current path. Place a full ground plane in microstrip line. Avoid slot in return plane (e.g. ground plane) Keep a symmetry (avoid unbalance in the return current path) Avoid routing of critical signals along board edge. CORRECT BAD January 18

Ensuring Signal integrity – Rule 4 If available, use on-chip techniques to improve signal integrity On-chip termination, programmable output driver impedance Pre-emphasis/De-emphasis, equalization (Xilinx) SSTL18 : I/O standard for DDR2 SDRAM 5Gbps - Without pre-emphasis 5Gbps - With pre-emphasis (Altera)

Crosstalk Example: voltage measurement at 3 terminals of two 20 cm long parallel PCB tracks. The first line is excited by a pulse generator, the second is terminated by two resistive loads. Origin of effects on both lines ?

Crosstalk Trace 1 (emitter) d Trace 2 (victim) W W I1’ I1 Crosstalk = near-field coupling I2 εr V h Parasitic return current path “Normal” return current path Evaluate the crosstalk in the case study. 15 January 18

Increase the isolation between emitter and victim lines
Guidelines for signal integrity Ensuring Signal integrity – Rule 5 Increase the isolation between emitter and victim lines Increase the distance between traces (rule 3 W = “the separation between traces must be 3 times the width of the trace as measured from centerline to centerline of two adjacent traces”) < 3W W W t h (εr = 4.5) Substrate ground 16 January 18

Guidelines for power integrity
Design guidelines for EMC Guidelines for power integrity January 18

Power Distribution Network Ensuring a stable power/ground voltage reference (ΔVdd < 5% Vdd nominal) Bulk capacitor (Low frequency) HF capacitor (ceramic) PCB – Power / ground plane Package and IC Power source Voltage converter / regulator Ferrite Vdd Vss Ground reference 1 µF – 10 mF 100 nF – 1 nF Contrainte : assurer une alimentation stable (toute fluctuation de tension  pertes de perf, dysfonctionnement (Vdd+/- 5 %) 1 nF Transistors, gates, interconnects 18 January 18

Power integrity (PI) issue Power supply source (regulator, DC-DC converter) ΔVdd PDN Vss Vdd i(t) Circuit PDN Noisy Integrated circuit Power supply bounce Delta-I noise ΔVss IR noise 19 January 18

Power integrity (PI) issue Example: Measurement of the power supply voltage fluctuation of a digital circuit High frequency contribution Low frequency contribution Switching Switching Switching Noise with a large frequency content and some major resonance modes 20 January 18

Ensuring power integrity – Rule 1 Maintain PDN impedance below the target impedance Equivalent model of a PDN (the most basic model…) PDN Circuit Vdd Power supply voltage bounce: ZPDN ΔVdd IIC gnd Ensuring power integrity relies on the control of a low impedance of the PDN. A target impedance ZT can be defined as a design objective: ZPDN Zt Frequency Target frequency range 21 January 18

Ensuring power integrity – Rule 2 Reduce interconnect parasitic (mainly inductance) of power and ground connections Use traces as wide as possible for Vdd and Vss connections i.e. use power and ground planes Be careful of the common impedance of Vdd and Vss connections (finite impedance, even for ground plane): Single point grounding with serial circuits Direct grounding to a reference ground plane 22 January 18

Ensuring power integrity – Rule 2 2.1) Use shortest interconnection to reduce the serial inductance Inductance is a major source of resonance Each conductor acts as an inductance Ground plane modifies inductance value (worst case is far from ground) Reducing inductance decreases SSN !! Lead: L=0.6nH/mm We detail four rules to reduce parasitic emission. The first one consists in decreasing the serial inductance. Inductance is a major component that creates resonance, and resonance is the source of conducted and radiated emission. The inductance is an intrinsic component of each conductor. When the conductor is far from ground, the inductance is increased. A bonding wire has approximately a 1nH/mm inductance. A supply line within the chip has a 0.2nH/mm inductance. Bonding: L=1nH/mm January 18

Ensuring power integrity – Rule 2 2.1) Use shortest interconnection to reduce the serial inductance Leadframe package: L up to 10nH Die of the IC bonding Long leads Far from ground PCB Flip chip package: L up to 3nH Short leads Die of the IC balls Add values for L package Close from ground Requirements for high speed microprocessors : L < 50 pH ! January 18

Case 2 : Texas Instruments OMAP3630 (Application processor)
Guidelines for power integrity Ensuring power integrity – Rule 2 2.2) Use enough Vdd/Vss pairs Case 1 : Micron T46H64M16LF Mobile LP DDR SDRAM Case 2 : Texas Instruments OMAP3630 (Application processor) 60 I/O pins, 8 power supply pins, 7 ground pins 515 I/O pins, 110 power supply pins, 80 ground pins January 18

Ensuring Power integrity – Rule 3 Add decoupling capacitor to reduce power supply bounce as close as possible from noise source (current demand) Principle: Voltage bounce v(t) Local charge tank Voltage regulator Decoupling capacitor IC Vdd Vss Vdd Vss PCB i(t) In time domain Large capacitors react rapidly to charge demand. In frequency domain Large capacitors reduce PDN impedance. 26 January 18

Ensuring Power integrity – How choosing decoupling capacitor ? If ideal capacitor, only one decoupling capacitor per power domain would be enough: Cdec: the minimum capacitor able to provide a current to the circuit without any large voltage fluctuations. ΔVddmax : max allowed voltage fluctuation ΔI : current peak absorbed by the circuit tr : rise time of the current peak 27 January 18

Ensuring Power integrity – How choosing decoupling capacitor ? Case study 2 : decoupling of FPGA power supplies. Two power domains: Core domain (1.2 V) and I/O domain (3.3 V) Transient current estimation: Core domain: Ipeak = 2 A during 10 ns I/O domain: 196 I/Os, typ. rise/fall time = 2 ns, typ. load = 20 pF Propose a budget of decoupling capacitors For Core domain: Cdec > 2*10n/(0.05*1.2) = 333 nF For I/O domain: for each I/O, the transient current is Iio = Cload*dV/dt = 20pF*3.3/2n = 33 mA  Iio_tot = 33m*196 = 6.5 A  Cdec > 6.5*2n/(0.05*3.3) = 78 nF. Cdec > N*Cload*Vdd/dVddmax where N = number of simultaneous switching I/O 28 January 18

Ensuring Power integrity – How choosing decoupling capacitor ? Case study 2 : decoupling of FPGA power supplies. Recommendations from the manufacturer: Power domain Recommended decoupling capacitors Core 1x 100 µF, 5x 4.7 µF, 1x 470 nF I/O 4x 100 µF, 4x 4.7 µF, 6x 470 nF Plus all the recommendations about PDN routing and capacitor placement ! Here, the manufacturer is Xilinx (Spartan6). The FPGA is in version FT256 LX16 (BGA 256, 196 I/O, nearly CLB). See ug393 - PCB design and pin planning.pdf, Table 2-1. The manufacturer recommendation suggests to use larger capacitor than the one used in the simple calculation. Moreover, it suggests to use a lot of capacitors (since they are numerous Vdd/Vss pins). The rpoblem with our simple formulation is that it does not consider the intrinsic parasitic elements of capacitors, that limit either their rapidity to deliver charge, or their frequency range. 29 January 18

Ensuring Power integrity – Real decoupling capacitors Impedance profile in frequency domain: X7R 50 V ceramic capacitors On which frequency range are these decoupling capacitors really efficient ? 100 µF electrolytic capacitor 30 January 18

Ensuring Power integrity – How choosing decoupling capacitor Methodology to optimize the choice of decoupling capacitors: Board model Regulator model Circuit(s) model Define Zt PDN without decoupling model Define freq. range of decoupling Fmin  Fmax Compute ZPDN YES If ZPDN(f) > Zt for f in [Fmin;Fmax] NO Add capacitor(s) and/or change capa values Capacitors model Power integrity OK – Decoupling budget January 18

Board + IC without decap
Guidelines for power integrity Ensuring Power integrity – How choosing decoupling capacitor Example: decoupling of a 16 bit microcontroller (dspic33F). The circuit produces a significant amount of noise over the range 1 – 500 MHz. We select Zt = 2 Ω. IC Current (1 Ω probe) Z PDN (VNA measurement) Board + IC without decap ZT The max current is 76 dBµA  6.3 mA. If Zpdn = 2 ohms, the voltage fluctuation = 12.6 mV. With 6×100 nF decap 32 January 18

Ensuring Power integrity – Anti-resonance issue What happens if 2 “real” capacitors are placed in parallel ? Fantires The impedance around the antiresonance frequency can be computed as follows: C1 is very small compared to L1 (L1 and C1 have already resonated, at 22 MHz). The equivalent circuit, if the resistances R1 and R2 are neglected, becomes L2 and C2 in serie, with L2 in parallel. The equivalent impedance is : Z (f=Fantires) = j*L1*w*(1-L2C2*W²)/(1-(L1+L2)*C2*w²), w = 2*pi*freq. When w² = 1/((L1+L2)*C2), Z becomes infinite, this is the antiresonance. Fantires = 2*pi/sqrt((L1+L2)*C2) = 50 MHz The impedance does not become infinite due to the capacitor ESR, but the impedance reaches a local maximum, which could be larger than the target impedance. If a current (delivered by the circuit itself or an external disturbance source) excites this circuit at the antiresonance frequency, a large voltage fluctuation can be produced. Fantires = 33 January 18

What is the cause of this anti-resonance ?
Guidelines for power integrity Ensuring Power integrity – Anti-resonance issue Example: power integrity of a 16 bit microcontroller (dspic33F) with 6×100 nF X7R decoupling capacitor. The PDN impedance measurement shows an anti-resonance at 162 MHz PDN equivalent model Fantires The model is formed by: the board model (the cavity formed by Vdd and Vss planes), the 6 * 100 nF decoupling capacitors (we model them by an equivalent capacitors) and the circuit model (on-chip capacitor and package inductance). The element values have been determined from VNA measurements. If we analyze the circuit, the anti-resonance is produced by the on-chip capacitor (Cchip) and several inductive contribution: package inductance (Lpackage), board and decoupling capacitor inductances (Lboard // LCdec). Actually, as Loboard >> LCdec, the board inductance has only a small contribution. According to this model, the anti-resonance frequency should be equal to: Fantires = 2*pi/sqrt((Lpackage+LCdec)*Cchip) = 168 MHz. This anti-resonance is linked to several elements of the PDN. The circuit has an important contribution on the appearance of this anti-resonance. What is the cause of this anti-resonance ? January 18

Ensuring Power integrity – Anti-resonance issue Example: power integrity of a 16 bit microcontroller (dspic33F) with 6×100 nF X7R decoupling capacitor. Measurement of power supply voltage in time domain (16 I/O pads switch simultaneously). The oscilloscope capture shows the output signal of a I/O pad (C2), which switches at 5.7 MHz, and the power supply voltage measured on Vdd power plane (C1). At each I/O switching, a voltage bounce appears. IT looks like a oscillatory signal with a constant pseudo-period which is damped after several period. If we analyze in detail this pseudo-oscillation, we could verify that its frequency is about 162 MHz, the anti-resonance frequency of the PDN. The circuit activity produces a current that circulated across the PDN. The circuit current has large spectrum (see slide 25, from 1 to 500 MHz). The spectral content between 1 and 100 MHz is correctly filtered by the small PDN impedance. However, the noise produced around 160 MHz is not filtered by the PDN because of the antiresonance. The circuit is able to activate this resonance mode, so that’s why we see clearly an oscillation with such a frequency. Even if the PDN impedance tends to increase, the contribution of higher harmonics is not visible because the current amplitude tends to rapidly falls down. The different elements of the PDN introduced some losses, so that’s why the oscillatory is damped quite rapidly. January 18

Ensuring Immunity – Anti-resonance issue Example: power integrity of a 16 bit microcontroller (dspic33F) with 6×100 nF X7R decoupling capacitor. Measurement of conducted immunity (harmonic signal coupled on power supply plane according to DPI standard). At each harmonic frequency, the disturbance power is increased until a circuit failure arises. Max. Power This antiresonance alters also the immunity of the circuit to conducted interferences. Here an harmonic conducted interference is coupled to the Vdd plane of the dspic test board. At several frequency, the amplitude of the disturbance is increased until a failure arises. The circuit presents a failure at a lower level around 160 MHz. This weakness is not intrinsic to the circuit, but linked to the anti-resonance of the PDN. At this frequency, for a given disturbance amplitude, a larger voltage fluctuation is coupled on Vdd plane.

Guidelines for reduced radiated emission
Design guidelines for EMC Guidelines for reduced radiated emission January 18

Radiated emission – basic mechanisms Radiated emissions come from interconnects excited by a transient current or voltage. They become parasitic antennas. Two basic radiated mechanisms: Dipole antenna (electric) high impedance load (I/O loaded by high impedance) E field proportional to length l Loop antenna (magnetic) Low impedance load (power supply, I/O loaded by low impedance H field proportional to surface S Electric field Magnetic field Circuit I Circuit Clock VSS VDD Length l High Z load Surface S 38 January 18

Reducing radiated emission – Rule 1 Reduce parasitic antenna (length or surface) to reduce differntial and common mode radiation Identify current loops on PCB and reduce their surface. Place decoupling capacitors as close as possible to IC pins. Use power or ground plane to reduce current loop surface. Reduce the length of interconnects which carry high frequency signals. Circuit Circuit VDD VDD Decoupling capacitor VSS VSS Decoupling capacitor Id Id Large loop  High radiated differential mode Smaller loop  Reduced radiated differential mode 39 January 18

Control the current return path to reduce common mode
Guidelines for reduced radiated emission Reducing radiated emission – Rule 2 Control the current return path to reduce common mode Example 2: one differential output buffer with a non symmetrical routing Example 1: one Vdd pin but two Vss pins IVdd = IVSS1+IVSS2 Power Differential buffer I+ ≠ I- Circuit IVdd I+ VDD VSS2 D+ VSS1 IVss1 D- I- Parasitic coupling GND IVSS2 Ic 40 January 18

Use a “good” ground plane(s) to shield noisy interconnects
Guidelines for reduced radiated emission Reducing radiated emission – Rule 3 Use a “good” ground plane(s) to shield noisy interconnects Use coplanar or stripline configuration to shield noisy interconnect. A “good” reference plane is equipotential at any point ! Connect two reference plane witth same potential by vias regular interval less than λ/20 ! Correct connection between two planes with same potential Stripline configuration Ref plane line GND via Ref plane GND 41 January 18

Radiated emission – Case study – Student project Basic digital applications routed on a 2 layer board with the auto-router function of the board design tool. Only one 100 nF decoupling capacitor for all the application. Measurement of radiated emission in TEM cell. Limit CISPR25

Radiated emission – Case study – Student project Numerous EMC design rules violation: large power-ground loops, long fast clock interconnect, return path not ensured by a ground plane… Change the placement & routing of the board by starting to place Vdd/Vss and fast clock, add a ground plane on both side. Design rule violation examples: Large loop CMOS inverter Vdd connection Vss connection Equivalent surface of fast clock interconnect “High speed” clock source 43

Radiated emission – Case study – Student project Top layer Effect of placement & Routing improvement (still one 100 nF decoupling capacitor) -30 dB Bottom layer 44 January 18

Design guidelines for EMC
Reduction of I/O noise January 18

Reduction of I/O noise f
Rule1: As I/Os are one of the most contributor to radiated or conducted emission, reduce I/O noise Reduction of the fast rate of I/O current. Minimize the number of simultaneous switching lines (bus coding) Reduce di/dt of I/O by controlling slew rate and drive Tr1 Tr2 SR & Drive control Emission level f 1/Tr2 1/Tr1 January 18

Full Drive – High slew rate Reduced Drive – High slew rate
Reduction of I/O noise Reduce I/O noise – Case study Example: I/O buffer with Drive and slew rate control options: Full or reduced drive, high and limited slew rate. Impact of I/O options on timing waveform: Rise time = 2 ns Rise time = 8.6 ns Full Drive – High slew rate Reduced Drive – High slew rate January 18

What is the more « emissive » option ? The less emissive ?
Reduction of I/O noise Reduce I/O noise – Case study Impact of I/O options on timing waveform and output drive current: What is the more « emissive » option ? The less emissive ? January 18

Reduction of I/O noise Reduce I/O noise – Case study
Comparison of conducted emission (1 ohm method)

Reduction of I/O noise Reduce I/O noise – Case study
Comparison of conducted emission (1 ohm method) January 18

Spread-spectrum frequency modulation
Design guidelines for EMC Spread-spectrum frequency modulation January 18

Spread spectrum frequency modulation
Frequency modulation spreads the spectrum of a signal Example : sinus clock at Fc = 100 MHz vs modulated sinus clock: Carrier frequency Fc = 100 MHz Modulation frequency FM = 1 MHz Frequency excursion dF = +/- 5 MHz  Modulation index md = 5 Reduction of narrow band RF energy Spread spectrum over B In this example, md = dF/Fm = 5 and Fm = 1 MHz. According to Carson rule, the bandwidth of the modulated signal is nearly: B = 2*1e6*(1+5) = 12 MHz, which is confirmed by the experimental result. Carson rule: 52 January 18

Rule1: Reduce noise from clock or PWM signals by using Spread Spectrum Frequency Modulation (SSFM) Principle: Unmodulated clock (carrier) Freq. modulation ΔF Clock in Clock out Tc Tc+/-dt +/- dt Frequency Modulated clock Modulant t Carson rule applies also (for fundamental frequency): TMod dP Modulated clock What is the amplitude reduction? B Unmodulated clock 53

Emission improvement The reduction of spectrum amplitude depends on: Parameters of the modulation (md and Fm) The modulant waveform (selection of a waveform that makes the spectrum as flat as possible) Receiver bandwidth RBW: P RBW dP P Measured SSFM signal unmodulated EMI receiver f SSFM B P The SSFM can also be limited by constraints on the clock. For example, SSFM on a clock produces jitter that must be limited for digital circuit and asynchronous bus to prevent timing errors. For audio class-D amplifier, SSFM can degrade the harmonic distortion. Measured SSFM signal f RBW B f 54 B

Case study – Class-D amplifier MAX9768 Two output modulations: Classic PWM mode Filterless modulation mode Three operating modes: Fixed frequency (300 or 360 kHz) SSFM (Fc = 300 kHz, df = +/- 7.5 kHz) External clock (1 to 1.6 MHz) Rather than depend on an external LC filter to extract the audio signal from the output, Maxim's filterless Class D amplifiers rely on the inherent inductance of the speaker load and the human ear to recover the audio signal. When using filterless Class D amplifiers, the speaker load should remain inductive at the amplifier's switching frequency to achieve maximum output-power capabilities. One disadvantage of filterless operation is the possibility of radiated EMI from the speaker cables. Because the Class D amplifier output waveforms are high-frequency square waves with fast-moving transition edges, the output spectrum contains a large amount of spectral energy at the switching frequency and integer multiples of the switching frequency. Without an external output filter located within close proximity of the device, this high-frequency energy can be radiated by the speaker cables. Maxim's filterless Class D amplifiers help mitigate possible EMI problems through a modulation scheme known as spread-spectrum modulation. Spread-spectrum modulation is accomplished by dithering or randomizing the switching frequency of the Class D amplifier. The switching frequency is typically varied up to ±10% of the nominal switching frequency. While the period of the switching waveform is varied randomly cycle-to-cycle, the duty cycle is not affected, thereby preserving the audio content of the switching waveform. Rather than having the spectral energy concentrated at the switching frequency and its harmonics, spread-spectrum modulation effectively spreads out the spectral energy of the output signal. In other words, the total amount of energy present in the output spectrum remains the same, but the total energy is redistributed over a wider bandwidth. While it is possible that some spectral noise may redistribute into the audio band with spread-spectrum modulation, this noise is suppressed by the noise-shaping function of the feedback loop. While spread-spectrum modulation significantly improves EMI performance of filterless Class D amplifiers, there is typically a practical limit on the length of the speaker cables that can be used before the device begins to fail FCC or CE radiated-emissions regulations. If a device fails radiated-emissions tests due to long speaker cables, an external output filter may be needed to provide additional attenuation of the high-frequency components of the output waveform. In many applications with moderate speaker cable lengths, ferrite bead/capacitor filters on the outputs will suffice. EMI performance is also very layout sensitive, so proper PCB-layout guidelines should be strictly followed to guarantee compliance with applicable FCC and CE regulations. 55 January 18

Case study – Class-D amplifier Observe the effect of the internal SSFM on the fundamental frequency of the common-mode noise which propagates along the speaker cable. Use a narrow RBW. Observe the effect of the internal SSFM on the spectrum of the common-mode noise which propagates along the speaker cable. Use a narrow RBW. EN55022 recommends the following RBW: 9 kHz from 150 kHz to 30 MHz 120 kHz from 30 MHz to 1 GHz What is the effect of the internal SSFM on the conducted emission? 56 January 18

Case study – Class-D amplifier How could you improve the conducted emission reduction ? Identify the optimal waveform to reduce the conducted emission. Validate it on the MAX9768 class-D amplifier. 57 January 18

Design guidelines for EMC of electronic devices

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