1. Impiego dei MAPS per l’upgrade dell’ITS
Alessandra Lattuca
Università degli studi di Torino – INFN (To)
Tor Vergata - Rome, April 10, 2015
On behalf of the ALICE Collaboration
Impiego dei MAPS per l’upgrade dell’ITS

2. outline Background and Motivations for the ALICE ITS UPGRADE
Overview of the Monolithic Active Pixel Sensor (MAPS) technology
High Speed Data Transmission
Summary

3. Alice detector
Main goal: detailed study of the quark-gluon plasma (QGP) Produced in heavy ion collisions

4. The present inner tracking system
Primary vertex Localization
Secondary vertex reconstruction
Particle Identification
Layer
Type
r (cm)
±z (cm) 1
Hybrid pixel
3.9
14.1 2
7.6 3
Drift
15.0
22.2 4
23.9
29.7 5
Strip
38.0
43.1 6
43.0
48.9
Limitations:
Read-out rate Capability is 1 kHz;
Material Budget per layer: 1.14%X0

5. The NEW ITS INNER BARREL OUTER BARREL Layer Type r (cm) z (cm) INNER
Inner Layers
MAPS
2.24 – 2.67
27.1 1
3.01 – 3.46 2
3.78 – 4.21
OUTER BAR
Middle 3
19.44 – 19.77
84.3 4
24.39 – 24.70
Outer Layer 5
34.23 – 34.54
147.5 6
39.18 – 39.49
Material Budget per layer 0.3%X0 (Inner Barrel)
Read out rate: 50kHz

6. Standard Maps Thin Sensor  Thermal diffusion
N-well collection diode 
NO P-Mos transistors allowed 

7. DEEP PWELL for P-Mos implementation 
Quadruple well Maps
TowerJazz 0.18 µm CMOS technology
Improved TID due to the smaller technology node (Gate oxide < 4 nm)
High resistivity epitaxial layer. The resistivity ranges between 1 kΩ ∙cm and 6 kΩ ∙cm so that a sizeble part of the sensor volume can be depleted
Thermal diffusion + Reverse Bias application to speed up the collection time
N-well collection diode
6 metal layers option in order to have high density and low power digital circuits
DEEP PWELL for P-Mos implementation 

8. Alpide Chip Matrix of 512 rows x 1024 columns
Until now, 2 prototypes of ALPIDE were fabricated and a third version is under development
Pixel dimension (pAlpide1 e pAlpide2): 28 x 28 µm2
4 different pixel flavours
New Low Power Priority Encoder read-out architecture

9. Last Prototype of Alpide
SLOW CONTROL & CLK DISTRIBUTION
DTU

10. High Speed DATA Transmission
Phase Locked Loop (PLL) + Serializer + Low Voltage Differential Signaling (LVDS) Driver
The DTU will be implemented for both ITS chip design options, ALPIDE and MISTRAL –O
Send data from the chip periphery to the patch panel
Need to drive data at :
the targeting speed of 1.2 Gbps along a 0.3 m Al Flex Printed Citcuit + 5m Cu twinax cable (Inner Barrel);
the targeting speed of 400 Mbps along a 1.5 m Cu Flex Printed Circuit + 5m Cu twinax cable (Outer Barrel)

11. Data Transmission Unit (DTU) Block Diagram

12. LVDS : PRINCiple of operation
LVDS : Low Voltage Differential Signaling (TIA/EIA-644)
Current steering Principle
Less sensibility to the common mode noise
Less EMI

13. ANALyzing the transmission: eye diagram

14. First version – Submitted in March2013 with an engeenering run to which cern contributed
DRIVER
Additional switches for the Slew rate Control

15. 2 LVDS Driver variants Submitted in march 2013 & tested in september 2013
LVDS CHIP 1
LVDS CHIP 2
The difference between the two chips is in the receiver part. For the LVDS chip 1 the current which flows in the receiver has a fixed value of 1mA . In contrast, for LVDS chip 2 it possible to select the current which flows in the circuit.

16. Bit rate (Mbps)
400
Diff. Amplitude (mV)
494
Unit Interval (ns)
2.5
Eye Width (UI)
0.99
Eye Height (mV)
457
Rise time (ps)
198
Fall time (ps)
183
Jitter (ps)
0.014
Current (mA) 4
Bit rate (Mbps)
1000
Diff. Amplitude (mV)
450
Unit Interval (ns) 1
Eye Width (UI)
0.93
Eye Height (mV)
400
Rise time (ps)
151
Fall time (ps)
144
Jitter (ps)
0.11

17. Transmission quality degrades by increasing the transmission speed and reducing currents

18. LVDS-Block Diagram – engeenering run November 2014Z

19. Pre- Emphasis A A_D A A_D I_Out -IMD 1 -IMD-IPE IMD+IPE IMD
-IMD 1
-IMD-IPE
IMD+IPE
IMD
Pre-emphasis is needed to overcome RC limitations of the long transmission lines.
We will add/subtract a small amount of current ONLY if two subsequent bits are different. For this reason we need to know the bit stream A and its delayed copy A_D

20. Vertical Aperture (mV)
POST Twinax
Parameter
Value
Hor. Aperture (ps)
746.6
Vertical Aperture (mV)
564.6
tr (ps)
516
tf (ps)
535
bit period
827.3
jitter
67.2
Simulation Conditions:
Calibre view
Nominal Corners
Driver Code: 9 (4 mA)
Pre-Emphasis Code: 4 (2mA)
30 cm Al FPC + 5m Coax Cab.
Bit rate: 1.2 Gbps

21. LVDS TEST CHIP Submitted in November 2014
LVDS driver test chip submitted in November
The driver will be tested by using:
A clock from the PLL
An external PRBS and the same signal delayed
FUTURE PLAN: SUBMISSION in APRIL 2015
On the next prototype we will include the driver without SR control in the full DTU chain (PLL + HS Serializer + Driver)

22. Summary and conclusion
ITS Upgrade;
MAPS technology;
High Speed Data Transmission: so far two LVDS driver standalone were submitted. At the end of April 2015 the entire DTU will be integrated on the third version of ALPIDE;
The first LVDS driver prototype were tested where the second prototype submitted in November 2014 will be tested in few weeks from now.
The R&D program for the ITS Upgrade will end in 2015 in order to be ready for the chips installation after the Long Shutdown 2, in 2018.

23. Thanks!

24. Bibliography
[1] The ALICE experiment at CERN LHC JINST 3 S08002
[2] Technical Design Report for the Upgrade of the ALICE Inner Tracking System (CERN-LHCC , 29 November 2013 )
[3] A. Tajalli, Y Leblebici, A slew controlled LVDS output driver circuit in 0.18 m CMOS technology, Solid-State Circuits, IEEE Journal of 44 (2),

25. Backup slides

26. present its limitation
Limited read-out capabilities : 1kHz with 100% dead time
Poor resolution on the distance of closest approach.

27. Hit densities

28. Limitations of the present ITS
First layer radius : 3.9 cm
Read out rate: 1kHz
Pixel Size: 50 x 425 µm2
Material Budget per layer: 1.14%X0
Power Consumption: 500 mW/cm2

29. HI-LHC: High Luminosity LHC projects
L = 2-3 x 1034 cm-2 s-1
Interaction rate = 50 KHz

30. Towards the new ITS First layer radius : 2.2 cm
Pixel Size: 28 x 28 µm2
Material Budget per layer: 0.3%X0
Power Consumption: < 300 mW/cm2
Read out rate: 50kHz

31. Specifications of the ITS
Parameter
Spec.
Unit
Line rate Inner Barrel
1.2
Gbps
Line rate Outer Barrel
400
Mbps
Load Termination
100 ± 10%
Ohm
T. Line
Lenght (mm)
Material
Model
FPC
300
Aluminium
MTline
Inner Barrel
Twinax
5000
Copper
Nport – S parameters
1500
Outer
Barrel

32. Characteristics LVDS DRIVER Param. Min Max VIS 0 V 1.8 V IOUT 2 mA
VOS (SS)
1 V
1.2 V
∆VOS (SS)
-50 mV
+ 50 mV
Bit Rate
400 Mbps
1200 Mbps
PRE-EMPHASIS
Param.
Min
Max
VIS
1.8
IOUT
1 mA
2.5 mA
Bit Rate
400 Mbps
1200 Mbps

33. Characteristics DRIVER Param. Min Max VIS 0 V 1.8 V IOUT 2 mA 8 mA
VOS (SS)
980 mV
1209 mV
∆VOS (SS)
-20 mV
+ 20 mV
VOS (PP)
150 mV
tpZH
0.35 ns
8.4 ns
tpZL
0.25 ns
0.7 ns
tpHZ
0.85 ns
1.3 ns
tpLZ
1.35 ns
RECEIVER
Param.
Min
Max
VICM
0 V
1.8 V
VIT+
50 mV
VIT-
-50 mV
VIS
LVDS
VOUT
0 V (L)
1.8 V (H)
tpEH
0.25 ns
0.55 ns
tpHD
0.7 ns
2.6 ns
Duty Cycle
46%
51%

34. Definition
VIS
Input Voltage Swing
VICM
Input Common Mode
VOS
Steady-state CM output voltage
∆VOS(SS)
Variation on the steady-state CM output voltage between logic states
VOS(PP)
Peak-to-peak common mode output voltage
VIT+, VIT-
Input voltage threshold
VOUT
Voltage at the receiver output
IOUT
Current driver by one driver
tPZH
Enable time, High impedence to high level output
tPZL
Enable time, High impedence to low level output
tPHZ
Disable time, High level to high impedence output
tPLZ
Disable time, Low level to high impedence output
tPEH
Enable time, Switch on to high level output
tPHD
Disable time, Switch off from the high level output

35. The inner tracking system (ITS)
Primary vertex Localization
Secondary vertex reconstruction
Particle Identification

36. TEST setup Agilent 81133A 3.35 GHz Pulse Pattern Generator
Tektronix MSO/DPO70000 Digital & Mixed Signal Oscilloscope
two 50 cm Cu coaxial cable