1. ENG2410 Digital Design “Cont .. Combinational Logic Circuits”
Fall 2017
S. Areibi
School of Engineering
University of Guelph

2. Resources Chapter #2, Mano Sections
2.6 Multi-Level Circuit Optimization
2.7 Other Gate Types
2.8 Exclusive-OR Operator and Gates
2.9 High Impedance Outputs
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3. Week #3 Topics NAND, NOR Universal Gates
AND-OR to NAND Implementations
XOR Gates, XNOR Gates
Odd/Even Parity
Logic Families
Electrical Characteristics3
Multiple Level Circuits
High Impedance Outputs
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4. NAND Gates
Very common for discrete logic

5. NAND is Universal
Any digital circuit can be designed and realized using AND, OR, NOT gates
If we can prove that NAND gate can emulate AND, OR, NOT, then we prove that it is Universal

6. NAND is Universal

7. NAND = AND-NOT = NOT-OR
Also reverse inverter diagram for clarity

8. NOR Gates
NOT OR
Also common
X Y Z
0 0
0 1
1 1 1

9. NOR also Universal
Dual of NAND

10. NAND and NOR Implementations
Digital circuits are frequently constructed with only NAND and NOR implementations:
Both are universal gates
they are easier to make (CMOS Technology)
Because of their use, rules have been developed that allow us to convert Boolean functions using AND, OR and NOT into the equivalent NAND and NOR logic diagrams.

11. Multilevel NAND Circuits
The general procedure for converting a multi-level AND-OR diagram into an all-NAND diagram is as follows:
Convert all AND gates to NAND gates with AND-NOT graphic symbols
Convert all OR gates to NAND gates with NOT-OR graphic symbols
Check all the bubbles in the diagram
Every bubble that is not compensated by another along the same line will require the insertion of an inverter or complement the input literal

12. Sum of Products with NAND
Easy to think of bubbles as canceling

13. AND-OR Circuit Easy to Convert

14. Exclusive-OR Function
Exclusive-OR (XOR) performs the following function
x  y = xy’ + x’y
This function is equal to one only if either x or y is equal to one but not both.
Another name for the XOR is the ODD FUNCTION!!

15. Exclusive OR
Exclusive OR
Symbol is 
Plus in a circle

16. Each Module uses XOR

17. XOR Implementations

18. Equivalent Expression
XNOR Function
Description 
Output Y is FALSE if input A OR input B are TRUE Exclusively, else it is TRUE.
Logic Symbol  A B Y
XNOR
The complement of an XOR function is an XNOR (even function)
Truth Table 
Y =
Equivalent Expression
A  B
Boolean Expression 

19. Buffer No inversion No change, except in power or voltage
Used to enable driving more inputs

20. Binary Signaling (Noise Margin)
Zero volts
FALSE or 0
5 volts
TRUE or 1
Noise

21. Tri-State Output w/ 3 states: H, L, and Hi-Z High impedance
Behaves like no output connection if in Hi-Z state
Allows connecting multiple outputs

22. Multiplexed with Hi-Z
Normal operation is blue area
Smoke

23. Electrical Characteristics
Fan in – max number of inputs to a gate
Fan out – how many standard loads it can drive (load usually 1)
Voltage – often 1.8v, 3.3v or 5v
Noise margin – how much electrical noise it can tolerate
Power dissipation – how much power chip needs
TTL high
Some CMOS low (but look at heat sink on a Pentium)

24. Propagation Delay Max of high-to-low and low-to-high
Maximum and typical given

25. Week #3 Part (b) Cont .. Combinational Logic Design
ENG241 Digital Design
Week #3 Part (b)
Cont Combinational Logic Design
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26. Resources Chapter #3, Mano Sections 3.1 Design Concepts and Automation
3.2 The Design Space
3.3 Design Procedure
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27. Week #3 Topics Combinational Circuits Analysis versus Design
Design Hierarchy
CAD Tools
Design Procedure
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28. Combinational Circuits
A combinational logic circuit has:
A set of m Boolean inputs,
A set of n Boolean outputs, and
The output depends only on the current input values
No Feedback, no cycles
A block diagram:
m Boolean Inputs
n Boolean Outputs
Combinatorial
Logic
Circuit
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29. Sequential Circuits
A sequential circuit consists of combinational circuits to which storage elements are connected to form a feedback path.
Storage elements store binary information.
Outputs of a sequential circuit are a function of the inputs and the internal state of the storage elements.
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30. Analysis vs. Design
Design of a circuit starts with specification and ends up with a logic diagram.
Analysis for a combinational circuit consists of determining the function that the circuit implements with:
A set of Boolean functions or
A truth table, together with a possible explanation of the operation of the circuit.
We can perform the analysis by manually finding the Boolean equations or truth table.
The first step in the analysis is to make sure that the given circuit is combinational and not sequential (i.e. no feedback or storage elements).
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31. Derivation of Func. Or Table
Label gate outputs of input variables
Determine Boolean functions or values
Label outputs of gates fed by previously labeled gates
Determine Boolean function or values
Repeat 2 until done

32. Let’s do this Example

33. Cont .. Analysis Example

34. Derivation of Truth Table
Make table with 2n rows, where n is number of inputs
Label some gate outputs
Put those labels and the final outputs on columns of truth table
Work your way across

35. Derivation of Truth TableC D T1 T2 T3 T4 F1 F2 1

36. Design Procedure Specification
Write a specification for the circuit if one is not already available
Formulation
Derive a truth table or initial Boolean equations that define the required relationships between the inputs and outputs, if not in the specification
Optimization
Use K-Maps to simplify Boolean Expression.
Draw a logic diagram or provide a netlist for the resulting circuit using ANDs, ORs, and inverters

37. Design Procedure HOW TO DEAL WITH A LARGE DESIGN? Technology Mapping
Map the logic diagram or netlist to the implementation technology selected (FPGA, PCB)
Verification
Verify the correctness of the final design
HOW TO DEAL WITH A LARGE DESIGN?

38. Design Hierarchy Just similar to large software development:
To design a large chip we need hierarchy
Divide and Conquer
To create and also to understand
Block is equivalent to object

39. Example – 4-bit Comparator
Specifications:
Input: 2 vectors A(3:0) and B(3:0)
Output: One bit, E, which is 1 if A and B are bitwise equal, 0 otherwise
Straight forward implementation??

40. Formulation
Since the circuit has eight inputs, use of truth table for formulation is impractical!
We need to create a truth table with 256 entries!!
In order for A[3:0] and B[3:0] to be equal, the bit values in each of the respective positions, 3 down-to 0, of A and B must be equal.
Use intuition to immediately develop a multiple level circuit. How?

41. Design Use Hierarchical Design: Decompose the problem into:
Four 1-bit comparison circuits (i.e., One Module/bit)
An additional circuit that combines the four comparison circuit outputs to obtain E (i.e., Final Module for E)

42. Design for MX module Logic function is Can implement as
Define the output of the circuit to be:
`0’ if both inputs are similar and
`1’ if they are different? Ai Bi Ei 1
Logic function is
Can implement as

43. 4-bit comparison?? E

44. Design for ME module
Final E is 1 only if all intermediate values are 0 So
And a design is
Design for MX module Ai Bi Ei 1

45. Overall Design

46. CMOS Technology

47. Semiconductor Materials
Electronic materials generally can be divided into three categories:
Insulators
Semiconductors
Conductors
The primary parameter used to distinguish among these materials is the resistivity (rho)
Insulator < rho
Semiconductors 10-3 < rho < 105
Conductors rho < 10-3
Silicon and germanium are the most important semiconductor materials

48. P-type and N-type
The real advantage of semiconductors emerge when impurities are added to the material in minute amounts (Doping)
Impurity doping enables us to change the resistivity over a very wide range and determine whether the electron or hole population controls the resistivity of the material.
Donor Impurities: have five valence electrons in the outer shell (phosphorus and arsenic). Semiconductors doped with donor impurities are called n-type.
Acceptor Impurities: have one less electron than silicon in the outer shell (boron). Semiconductors doped with acceptor impurities are known as p-type.

49. Field Effect Transistor
MOSFET: Metal Oxide
Semiconductor
Field Effect Transistor
A voltage controlled device
Dissipates less power
Achieves higher density on an IC
Has full swing voltage 0  5V

50. The MOS Transistor
Polysilicon
Aluminum

51. nMOS Transistor |V GS |
An nMOS Transistor
Ids
Vgs

52. Transistor as a Switch
A Switch! |V GS |
An MOS Transistor

53. Implementing Logic using: nMOS vs. pMOS Devices

54. CMOS:Complementary MOS
Means we are using both N-channel and P-channel type enhancement mode Field Effect Transistors (FETs).
Why?

55. Complementary MOS (CMOS)
NMOS Transistors pass a ``strong” 0 but a ``weak” 1
PMOS Transistors pass a ``strong” 1 but a ``weak” 0
Combining both would lead to circuits that can pass strong 0’s and strong 1’s X Y C
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56. Complementary MOS (CMOS)
VDD
PUN and PDN are dual logic networks
In1
PMOS only
In2
PUN …
InN
F(In1,In2,…InN)
In1
In2
PDN …
NMOS only
InN
VSS
One and only one of the networks (PUN or PDN) is conducting in steady state
At every point in time (except during the switching transients) each gate output is connected to either VDD or VSS via a low resistive path
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57. CMOS Inverter
Pull-up Network A Y 1
Pull-down Network

58. CMOS Inverter A Y 1

59. CMOS Inverter A Y 1

60. CMOS Tri-State InverterY X Z 1 E Y E

61. Example Gate: NAND
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62. Example Gate: NOR
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63. End Slides

64. XOR Postulates and Theorems
Exclusive NOR (XNOR) can be generated by taking the complement of an XOR operation
(x  y)’ = xy + x’y’
The following identities apply to XOR (IMP!)
x  0 = x
x  1 = x’
x  x = 0
x  x’ = 1
x  y’ = x’  y = (x  y)’
XOR is also commutative and associative

65. XOR = Odd Function
The XOR operation with three or more variables can be converted into an ordinary Boolean function by replacing the  with its equivalent Boolean expression
A  B  C = (AB’ + A’B)C’ + (AB + A’B’)C
AB’C’ + A’BC’ + ABC + A’B’C
∑(1, 2, 4, 7)
This function is equal to 1 only if one variable is equal to 1 or if all three variables are equal to 1.
This implies that an odd number of variables must be one. This is defined as an odd function.

66. Error Detecting Codes Parity Good for checking single-bit errors 1 1 1
One bit added to a group of bits to make the total number of ‘1’s (including the parity bit) even or odd
Even
Odd
Good for checking single-bit errors
4-bit Example
7-bit Example 1 1 1 1 1 1

67. Parity Generation and Checking
XOR functions are very useful in systems requiring error-detection and correction codes.
A circuit that generates a parity bit is called a parity generator.
The circuit that checks the parity is called a parity checker.

68. Parity Generator Design even parity generator for 3-bit signal
Perhaps make truth table and K-Map
Draw with XOR, then sum-of-products w/ NAND gates
How do you design a detector?

69. Parity Bit ImplementationX Y Z P

70. Example 9-input odd function (parity for byte)
Basically checks for even parity!
Block for schematic is box with labels
Without hierarchy how would you start your design?

71. Design Broken Into Modules
Use 3-input odd functions

72. Use NAND to Implement XOR
In case there’s no XOR, for example

73. Components in Design
RHS shows what must be designed

74. Design Hierarchy

75. Design Example (continued)B C D A 1 3 2 4 5 7 6 12 13 15 14 8 9 11 10 X w z y x
Optimization
2-level using K-maps
W = A + BC + BD
X = BC + BD + B C D
Y = CD + C D
Z = D

76. Logic Families RTL, DTL earliest TTL was used 70s, 80s CMOS
Still available and used occasionally
7400 series logic, refined over generations
CMOS
Was low speed, low noise
Now fast and is most common
BiCMOS and GaAs
Speed