1. CHAPTER 4: MOS AND CMOS IC DESIGN
DDE 3253 – MICROELECTRONICS prepared by Assoc Prof Dr. Salwani Mohd Daud
CHAPTER 4: MOS AND CMOS IC DESIGN
Dec 06 - May 07

2. Introduction
Design processes are aided by simple concepts such as stick and symbolic diagrams
But the key element is a set of design rules.
Design rules are the communication link between the designer specifying requirements and the fabricator who materializes them.
Design rules are used to produce workable mask layouts from which the various layers in silicon will be formed or patterned
First set of design rules introduced here are lambda-based
They are ‘real’ and chips can be fabricated from mask layouts
Dec 06 - May 07

3. MOS layers
MOS design is aimed at turning a specification into masks for processing silicon to meet the specification
MOS circuits are formed on 4 basic layers: n-diffusion, p-diffusion, polysilicon and metal which are isolated from each other by thick or thin (thinox) silicon dioxide insulating layers
Polysilicon and thinox regions interact so that a transistor is formed when they crossed one another
In some processes, there may be a second metal layer or a second polysilicon layer.
Dec 06 - May 07

4. Stick diagrams
Stick diagrams may be used to convey layer information through the use of a color code
For example, NMOS design, green for n-diffusion, red for polysilicon, blue for metal, yellow for implant and black for contact
Dec 06 - May 07

5. Design rules and layout
The object of a set of design rules is to allow a ready translation of circuit design concepts usually in stick diagrams or symbolic form into actual geometry in silicon
The design rules are the effective interface between the circuits/system designer and the fabrication engineer
Lambda(l)-based design rules are based on the work of Mead and Conway
Based on a single parameter l which leads to a simple set of rules for the designer
All path in all layers will be dimensioned in l units and subsequently l can be allocated an appropriate value compatible with the feature size of the fabrication process
l can be allocated a value of 1.0 mm so that the minimum feature size on chip will be 2 mm (2l)
Dec 06 - May 07

6. Design steps The design steps are
Karnaugh map to define the specification
Boolean expression
Schematic diagram in transistor level
Stick diagram
layout
Dec 06 - May 07

7. MOS as a switch MOS is turned on or off depending on the gate voltage.
When turned on, a current can flow between drain and source.
The ‘on’ resistance in 100 W – 5 kW
The ‘off’ resistance is considered infinite; several MW
Dec 06 - May 07

8. MOS as a switch-cont.
Dec 06 - May 07

9. Good/strong 0 and poor 1-NMOS
When voltage gate is at zero, no channel exists so source is disconnected from the drain
When the gate is on Vgate = 1.0 V, channel exists
NMOS drives well at zero but poorly at the high voltage
The highest voltage of source is around 0.6 V that is VDD minus threshold voltage (VDD – VT)
N channel MOS device do not drives well logic 1 as shown in the figure.
Dec 06 - May 07

10. Good/strong 1 and poor 0-PMOS
PMOS gives approximately half the maximum current given by NMOS with the same device size.
The highest current is obtained with the lowest possible gate voltage,i.e. 0
PMOS is able to pass well the logic level 1
But the logic 0 is transformed into a positive voltage equal to the threshold voltage of the MOS device (VT = 0.35 V)
Dec 06 - May 07

11. Pass Transistors
Transistors can be used as switches
Dec 06 - May 07

12. Signal Strength Strength of signal
How close it approximates ideal voltage source
VDD and GND rails are strongest 1 and 0
NMOS pass strong 0
But degraded or weak 1
PMOS pass strong 1
But degraded or weak 0
Thus NMOS are best for pull-down network
Thus PMOS are best for pull-up network
Dec 06 - May 07

13. Transmission Gates Pass transistors produce degraded outputs
Transmission gates pass both 0 and 1 well
Dec 06 - May 07

14. Complementary CMOS Complementary CMOS logic gates
NMOS pull-down network
PMOS pull-up network
a.k.a. static CMOS
Dec 06 - May 07

15. Series and Parallel NMOS: 1 = ON PMOS: 0 = ON Series: both must be ON
Parallel: either can be ON
Series and Parallel
Dec 06 - May 07

16. Conduction Complement
Complementary CMOS gates always produce 0 or 1
Ex: NAND gate
Series NMOS: Y=0 when both inputs are 1
Thus Y=1 when either input is 0
Requires parallel PMOS
Dec 06 - May 07

17. Conduction Complement-NAND gate
Truth table for NAND gate
A B Y
0 0 1
0 1 1
0 1
1 1 0
PMOS
NMOS
Rule of Conduction Complements
Pull-up network is complement of pull-down
Parallel -> series, series -> parallel
Dec 06 - May 07

18. Compound Gates Compound gates can do any inverting function
Ex: AND-AND-OR-INV
Dec 06 - May 07

19. Compound Gates -cont
Dec 06 - May 07

20. Example:
A B C D Y AB CD 00 01 11 10 1
Dec 06 - May 07

21. Example: solution
Dec 06 - May 07

22. Exercises
Draw the transistor circuit diagram for the following outputs
Dec 06 - May 07

23. Solution for Q1
Dec 06 - May 07

24. Solution for Q2
Dec 06 - May 07

25. Solution for Q3
Dec 06 - May 07

26. Drawing stick diagram
Mask Layout and Stick Diagram for a CMOS Inverter
Dec 06 - May 07

27. Drawing stick diagram- transistor
A transistor exists where a polysilicon stick crosses either an N diffusion stick (NMOS transistor) or a P diffusion stick (PMOS transistor).
Note that there is no difference in the construction of a transistor source and a transistor drain. The source is determined as the source of conductors (electrons for NMOS / holes for PMOS) when current flows through the channel. In some pass transistor circuits, the source and drain may swap over during use.
Dec 06 - May 07

28. Drawing stick diagram- Implied Connections and Crossovers
Where two sticks of the same colour meet or cross there is always a connection.
Where two sticks of different colours meet or cross there is no implied connection.
Note that N and P diffusions may not cross each other. Where poly crosses diffusion we have a transistor
Dec 06 - May 07

29. Drawing stick diagram- Contacts
A connection may be explicitly defined using a filled black circle/rectangle.
In the general case a connection is permitted where the mask layers will be separated by just one layer of insulator (through which a "contact cut" may be defined). Thus P diffusion may connect to Metal1 but not directly to Metal2.
In a process where stacked contacts are permitted, we may draw a contact between non-adjacent conductors; e.g. between Poly and Metal3, in which case the connection to intermediate layers (Metal1 and Metal2) is implied.
Dec 06 - May 07

30. Drawing stick diagram- Taps
The tap represents a connection to something we can't see; either the N-Well (not shown on our stick diagram) or the wafer substrate.
A tap is defined using an unfilled black square. Here there will be only one conductor crossing the square (Metal1 power or ground rail).
An N-Well Tap is inferred where the connection is from a power rail while a Substrate Tap is inferred where the connection is from a ground rail.
Dec 06 - May 07

31. Drawing stick diagram- Combined Contacts and Taps
We can often save space by using a combined contact and tap. Here the tap shares the same Active Area as the contact.
A combined contact and tap is defined using a filled black square in place of the source contact (filled black circle).
A combined contact and tap can only be used where the end of a diffusion stick coincides with a contact to the power or ground rail.
Dec 06 - May 07

32. Drawing stick diagram- Colour Code
P diffusion
Yellow/
Brown
Metal 1
Blue
N diffusion
Green
Metal 2
Magenta/
Purple
Polysilicon
Red
Metal 3
Cyan/
Light Blue
Taps and Contacts
Black
Dec 06 - May 07

33. Mask layout
Use layout editor such as Microwind, Magic, Lasi – examples of open-source softwares
Commercial editors like silvaco
Dec 06 - May 07