1. Free Projects
For CENG 3430
CENG3430 Free Projects v.7c

2. CENG3430 Free Project- Requirement
Language and System: VHDL, Zedboard Board
Components: Input, Output, Main Unit, FSM
Group: Two students in one group
There will be no bonus if even you complete the project individually.
CENG3430 Free Projects v.7c

3. Marking Scheme Demonstration (60 %) Report (40 %)
Each group will be given 5-10 minutes to demonstrate your project to us. The project will be evaluated based on:
The techniques used in the project (20 %)
Completeness of the project (10 %)
Creativity of your project (10 %)
Presentation performance (20 %)
Report (40 %)
The whole project carries 40% of the coursework marks.
CENG3430 Free Projects v.7c

4. Deadline
Deadlines
Proposal (1 page) : 23:59,Monday, 27 March 2017, submit to eLearning.
The TA will discuss with your proposal on Tuesday, 28 March 2017 (lab time)
Demonstration:
Time: Tuesday, 18 April :30pm to 7:15pm
Venue: Lab 102.
Report: 23:59,Sat, 22 April 2017
CENG3430 Free Projects v.7c

5. Report Abstract Introduction Theory and design
Implementation and experimental result
Discussions
Conclusion
See the project specification for detail
CENG3430 Free Projects v.7c

6. Proposal (1 page) Project proposal Title Group members Objectives
Plan with time schedule
Additional equipment needed: Each group can buy additional components/equipment (not more than HKD300, keep the receipts, reimburse later though TAs) for the project , e.g. buying “pmod” cards for the zedboard, see
Search “pmod“ inside
Must get permission from the tutor before buying.
CENG3430 Free Projects v.7c

7. Project topic for reference
References
CENG3430 Free Projects v.7c

8. Example1 Ultrasonic radar
You can watch a short video of it at 
Source
Idea
count and display the time delay time between sending and receiving the sound package
Improvements: Can add more functions to the radar:
More user control,
Longer distance
Increase accuracy by averaging 10 counts
Send data to Linux for display
CENG3430 Free Projects v.7c

9. Example2 RS232 interface Source Idea: Improvements:
Idea:
Provided basic features of RS232 interface
Improvements:
Give more features
Error check: Parity check
Variable bitrate etc
CENG3430 Free Projects v.7c

10. Example3 Stepping motor interface
Source
Idea:
Control a small steeping motor by providing the clocking pulses
Improvements:
Build a small robot using it.
Interface Linux to the motors
CENG3430 Free Projects v.7c

11. Example 4: Joystick interface :Analogue input
Source
Be able to read the inputs from a variable resistor
Improvements:
Multi inputs
Link to Linux
CENG3430 Free Projects v.7c

12. Example 5a: VGA or HDMI interface
Source
Idea: generate timing signals for the display
Improvements:
Create some graphics or animation using this display
Link to Linux
A demo test has been performed, the file is at
CENG3430 Free Projects v.7c

13. Example 5b : VGA Connector on ZedBoard (By Simon Wong)
The ZedBoard allows 12-bit color video output through a through-hole VGA connector, TE Each color is created from resistor-ladder from four PL pins.
CENG3430 Free Projects v.7c

14. Example 5c: The VGA connections on the ZedBoard are defined in the XDC file as follow:#
# VGA Output - Bank 33
set_property PACKAGE_PIN Y21 [get_ports {B1}]; # "VGA-B1"
set_property PACKAGE_PIN Y20 [get_ports {B2}]; # "VGA-B2"
set_property PACKAGE_PIN AB20 [get_ports {B3}]; # "VGA-B3"
set_property PACKAGE_PIN AB19 [get_ports {B4}]; # "VGA-B4"
set_property PACKAGE_PIN AB22 [get_ports {G1}]; # "VGA-G1"
set_property PACKAGE_PIN AA22 [get_ports {G2}]; # "VGA-G2"
set_property PACKAGE_PIN AB21 [get_ports {G3}]; # "VGA-G3"
set_property PACKAGE_PIN AA21 [get_ports {G4}]; # "VGA-G4"
set_property PACKAGE_PIN AA19 [get_ports {HS}]; # "VGA-HS"
set_property PACKAGE_PIN V20 [get_ports {R1}]; # "VGA-R1"
set_property PACKAGE_PIN U20 [get_ports {R2}]; # "VGA-R2"
set_property PACKAGE_PIN V19 [get_ports {R3}]; # "VGA-R3"
set_property PACKAGE_PIN V18 [get_ports {R4}]; # "VGA-R4"
set_property PACKAGE_PIN Y19 [get_ports {VS}]; # "VGA-VS"
set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 33]];
CENG3430 Free Projects v.7c

15. Example 5d : Timing signals
Horizontal Sync HS – we need to generate a horizontal sync pulses to the monitor
Vertical Sync VS – we also need to generate a vertical sync pulses to the monitor
Pixel Clock (pixelclk) – Pixel clock is 25MHz clock derived from 100MHz clock (clk )
1us
37us
40ns
CENG3430 Free Projects v.7c

16. Example 5e : R,G,B data
R,G,B data – R, G and B pixels data are consists of 4 bits per color. The 4 bits RGB color data are converted to analog signal and output to the VGA connector.
CENG3430 Free Projects v.7c

17. Example 6: Sound generation
Source
Idea: produce sound from FPGA
Improvements:
Play music, or generate a song through this interface
Link to Linux
CENG3430 Free Projects v.7c

18. Example 7: Play with PMOD modules
Main Source
Small display
Pmod ACL: 3-axis Accelerometer
Microphone
Temperature sensor
CENG3430 Free Projects v.7c