1. Radiation Damage Tests at 1GRad Dose on 65nm CMOS transistors
Marlon Barbero – CPPM
Grzegorz Deptuch –FNAL -
The RD53 collaboration

2. Plan RD53 & CERN upgrades. Effect of radiation on CMOS.
Few results on test transistors.
Few results on ICs and blocks.
Conclusion.

3. RD53 collaboration
“Development of pixel readout IC for extreme rate and radiation” : ATLAS-CMS-CLIC working group on small feature size electronics (focus on one 65nm techno so far).
Goal:
Small pixels.
Very high hit rates.
Very high radiation levels.
Started with 1st meetings mid-2013.
6 working groups, among which one working group on radiation effects (Bergamo-Pavia, CERN, CPPM, Fermilab, LPNHE, New Mexico, Padova, but also others).
The work presented here essentially done in this framework.
See Valerio Re’s talk, Tuesday 20th

4. Pixel detectors upgrades
ATLAS IBL
ATLAS / CMS phase II
Main goal of this R&D!
Nominal: 1-2 GHz.cm-2, 1GRad, 1016 neutrons.cm-2, typ 50×50μm2, billion transistor 2×2 cm2 IC
CMS Phase I

5. Radiation effects in CMOS

6. Classical view of radiation effects in MOS
Focus here on the sensitive oxide (thin gate and FOX).
Reminder:
gate thickness 2.6nm.
hole mobility is << than e- mobility.
1st step: Radiation  e-/hole pair creation in oxide. Depending on biasing, electrons swept out in ~ps. Still fraction e- / holes recombine.
2nd step: Hopping hole transport to Si/SiO2 interface.
3rd step: Holes at interface  long-lived trap states.
4th step: Interface traps build-up.
Typical values (room T):
ref: Oldham (ionizing radiation effects in MOS oxides)

7. Notes on defect generation (I)
Which hole fraction recombines initially = fn (density -particle energy, particle type- and magnitude of field applied).
Deep hole trapping (in transition region where oxidation is incomplete). Annealing depends again on thickness, time, temperature and applied field. Annealing process == either tunneling (at ~ room temperature or below, neutralization by electron to Si+) or thermal
excitation (higher temp.).
Flat-Band Shift / Mrad dose function of oxide thickness in MOS cap
oxide thickness [nm]
ΔVFB shift / Mrad dose

8. Notes on defect generation (II)
Radiation-induced traps: Trivalent Si is passivated when oxide is grown by H. But radiation (or other type of stress)  depassivation (holes free proton reach interface and form H2 centers)== electrically active.
Annealing (in particular in thin oxides) might cure deep hole trapping component but not radiation-induced interface traps.
Vth vs annealing
ΔDit shift / Mrad dose
oxide thickness [nm]
Interface Traps Density Increase / Mrad dose function of oxide thickness
ref: Schwank (physical mechanisms contributing to device rebound)

9. Effect on drain current when radiation in MOS structure
particle
metal
ionization
pos. charge trapped in oxide
e-/hole creation
fixed charge
oxide
surface states
surface states
silicon
due to deep hole trapped + interface states
due to interface states

10. Radiation Induced Narrow Channel Effect -RINCE-
Trapping in STI of rad-induced positive charges opens inversion channel / parasitic transistor.
Strong dependence on width of transistor: for narrow transistors, influence of parasitic channels strong competitor to main channel.
ref: Faccio (radiation induced edge effect in deep submicron CMOS transistors)

11. A word from the past CMS / ATLAS current Front-End: ATLAS IBL (FE-I4):
250 nm technology.
~50 MRad.
Use of enclosed layout + guard rings. Custom libraries!!! If so, safe!
ATLAS IBL (FE-I4):
130nm.
~250 MRad.
Minimum W imposed. If so, safe!

12. Effects on test transistors: results

13. XRay irradiation at CERN
XRay irradiation, 10 keV, 150 kRad.min-1
T = -25°C
T = 25°C
T=100°C
T = -25°C
T = 25°C
T=100°C
First day : T=25°C
Mohsine Menouni et al, CPPM

14. NMOS threshold shift
A little decrease of the threshold for low dose level
-20 mV shift for the minimum width device
For levels of dose > 200 Mrad, the absolute value of Vth increases
At 1000 Mrad, the Vth shift is between 150mV to 320 mV depending on the device width (maximum for 240nm/60nm)
The Vth recovery at room temperature is very slow
Except at the beginning of annealing period and only for the narrowest devices (W=120nm and W=240nm)
High Temperature annealing (100 °C for 7 days) :
The Vth recovery is accelerated
The global Vth shift is < 200 mV
Reverse annealing behavior for the device with W=120nm (Vth first decreases and increases after)

15. Proton irradiation 3MeV proton -1016 neq.cm-2-, 3.6 - 36 MRad.min-1 ,
Lili Ding et al, Padova.

16. nmos transconductance variation
T = -25°C
T = 25°C
T=100°C
After 1000 Mrad : KPN loss is between 20% and 40%
The GM recovery at room temperature is very slow
100°C annealing : KPN loss decreases to reach a values between 25% and 8%
The loss is still higher for narrower devices
Menouni, CPPM

17. Ding, Padova

18. Notes on NMOS results
Note 3MeV p (Padova) neq.cm-2- vs 10 keV Xray (CPPM).
Note very different dose rate:
3.6 MRad.min-1 to 36 MRad.min-1 for Padova.
150 kRad.min-1 for CPPM / Xray box at CERN.
Different time cst for building of Q in oxide vs interface  Does this translate in much stronger influence of Qox contribution in Padova’s case (compensating interface charges)?  annealing studies!

19. pmos transconductance variation
T = -25°C
T = 25°C
T=100°C
For high level of dose (1000 Mrad), KPP decrease reaches 100% for 120 nm and 240nm devices
With annealing, devices recover the most part of GM loss
Wider devices recovers practically the pre-irradiation GM value
For the narrowest device, KPN variation is only 32% compared to the pre-irradiation value
Menouni, CPPM

20. pmos threshold shift Menouni, CPPM
T = -25°C
T = 25°C
T=100°C
Vth increases rapidly from a dose levels of 200 Mrad
Vth shift is < 120 mV for 1000 Mrad for wider devices and cannot be computed for narrower devices.
Vth is still increasing with annealing (reverse annealing)
Menouni, CPPM

21. Effects on IC and blocks: results

22. CPPM test of LBNL’s IC
When CPPM tested SEU in LBNL-dvp’ed 65nm proto (CERN PS)  Observed localized bits stuck in shift register used for pixel config. loading.
Hypothesis: TID effect /
Bit leaking.
Narrow pmos dose effect?
260 MRad to 310 MRad
390 MRad to 420 MRad
Pattern 1111
Pattern 1111
Rows 0-255
Rows 0-255
Tests with 24 GeV proton beam
Columns 0-15
Columns 0-15
CPPM / LBNL

23. Test IC dvped by CERN Sandro Bonacini, CERN
chip with digital logic blocks
Assembled with foundry standard cells, pads and IP blocks
Packaged, functional tests & irradiation measurements run on a custom test board
Shift-register
64 kbit, “DFQD1”
MinW=150nm for both p and n
Ring oscillator
1025 inverters “INVD0”
Wn=195nm, Wp=260nm
SRAM (from foundry compiler)
56 kbit
MinW = 90nm
Ring oscillator
Shift-register
SRAM
Sandro Bonacini, CERN

24. Low temp / high temp influence?
Bonacini, CERN
–25C
Ring oscillator 2011 test at 25C
-22% after irradiation 200Mrad
-13.8% after annealing
Ring oscillator 2014 test at –25C
For same sized inverter:

25. CLICpix TID / biasing effects in PMOS
XRay irradiation performed to 800 MRads.
DACs use PMOS switches to control a current mirror for each bit.
At high rates switches irradiated while they are ON (their control voltage is GND) degrade more quickly than the ones irradiated while they are OFF.
Above 200MRad, damaged switches are unable to let the nominal current pass (their driving current becomes too low).
400nm/1u
VDD
IDAC
>600 mV A A
~200 mV
Iout
Iout
Above 200 MRad.
Pierpaolo Valerio, CERN

26. BUT…
All I/O interfaces and digital structures did not show any significant degradation during irradiation, even after the analog front-end stopped working
The chips regained some functionality after two week of annealing at room temperature (the total power consuption went back to pre-rad value). Analog performances of the measured chip were found to be considerably degraded.
The measurement was performed at a dose rate of ~150 krad/minute (~75 krad/minute for the first 10 Mrads). The high dose rate could have an effect on the radiation damage and needs to be explored
Pierpaolo Valerio, CERN

27. Summary Unexplored territory in terms of process and radiation level.
Studies done so far on one 65nm technology mainly.
Gate effects / STI effects not clearly disentangled so-far.
NMOS: shift of Vth, drive capability loss… steep increase above 200 MRads. Still, provided one could handle degradation, depending on application, hint that devices might be operated to close to ~1GRad TID down to small W.
PMOS: Strong drive loss, narrowest devices completely off above few 100 MRads. Indication that narrowest devices will not work at close to 1GRad.
Effects seeing in test IC too.

28. Outlook
Still studies too preliminary and more work to be done in well-controlled conditions: Biasing for PMOS? Influence of temperature? Annealing scenario?
Then: Other damages type (Xray / neutron/ proton … investigate if DD becomes an issue). LDR vs HDR?
Relation to other stresses: NBTI, HCI…
If it is confirmed that damage is unacceptable, 2 ways out:
Other technologies (work starts on that topic, with limited momentum so far).
Rules for design to be established to allow intermediate dose level to be reached and replacement strategy.
Still to come later: SEE studies / Statistical spread after irrad / Modelling after irrad /etc…

29. BACKUP
BACKUP

30. Core NMOS radiation performance
Threshold voltage shift
Leakage current
Up to ~20mV shift for 200 Mrad
Some rebound effect visible for narrow devices
in 130nm: was 150mV
At high doses Vth shift is positive for wide devices, negative for narrow devices
STI edge oxide traps considerable charge (RINCE)
Subtreshold slope does not change significantly
Less than 10× increase in leakage for wide devices (W > 360nm)
Narrow devices have up to 2.5 orders of magnitude increase
In 130nm:
All devices are peaking at ~100nA
Narrow devices increase leakage by 3 orders of magnitude
Ileak is Mrad
Sandro Bonacini - PH/ESE -

31. Core PMOS: Vth shift and gm loss
gm,max
PMOS Vth shift limited to 60 mV
trapped charge and interface states sum up
More evident for narrow devices
Less than 10mV for transistors with W>1um
Compared to other technologies
Better performance than 130 nm
had up to
30mV for wide devices
In a 90 nm tech we observed a similar effect: 200Mrad
Radiation kills maximum gm,max (strong inversion)
...but not gm in weak inversion region
Sandro Bonacini - PH/ESE -