1. APEC 2010
THE APPLIED POWER ELECTRONICS CONFERENCE AND EXPOSITION
February 21-25, 2010, Palm Springs, USA
Three-phase Voltage Doubler Rectifier Based on Three-Switching Cell For Uninterruptible Power Supply Applications Using FPGA
Raphael A. da Câmara -
Paulo P. Praça, Cícero M. T. Cruz, René P. Torrico-Bascopé,
Carlos E. A. Silva, Demercil D. S. Oliveira Jr., Luiz H. S. C. Barreto
Federal University of Ceará - Brazil 1

2. INTRODUCTION
Power Eletronics has achieved an important level at new technologies development
UPS provide eletricity adequately with quality for:

3. INTRODUCTION An UPS can be classified into three types: On-Line
It’s most suitable for critical loads.
Interactive
Stand-By

4. INTRODUCTION
Typical single-phase On-line UPS topology

5. INTRODUCTION
Typical single-phase On-line UPS topology with HF isolation

6. INTRODUCTION
Typical single-phase On-line UPS topology

7. INTRODUCTION
Typical single-phase Three-Level Voltage Doubler Boost topology

8. INTRODUCTION Single-phase Voltage Doubler Boost topology based
on Three-State Switching Cell

9. INTRODUCTION The focus of this paper is presents
an alternative AC-DC Three-phase converter for UPS with:
Power Factor Correction;
Reduced current stress on semiconductors devices;
Reduced volume and weight of the magnetic comp.;
Simple control strategy using FPGA.

10. PROPOSED TOPOLOGY Single-phase Voltage Doubler Boost topology based
on Three-State Switching Cell

11. PROPOSED TOPOLOGY
Proposed Three-phase Voltage Doubler Boost topology based
on Three-State Switching Cell

12. CONVERTER OPERATION MODES IN EACH PHASE

13. CONVERTER ANALYSIS TO NON-OVERLAPPING MODE
1st stage (t0 ≤ t ≤ t1)

14. CONVERTER ANALYSIS TO NON-OVERLAPPING MODE
2nd stage (t1 ≤ t ≤ t2)

15. CONVERTER ANALYSIS TO NON-OVERLAPPING MODE
3rd stage (t2 ≤ t ≤ t3)

16. CONVERTER ANALYSIS TO NON-OVERLAPPING MODE
4th stage (t3 ≤ t ≤ T)

17. CONVERTER ANALYSIS TO OVERLAPPING MODE
1st stage (t0 ≤ t ≤ t1)

18. CONVERTER ANALYSIS TO OVERLAPPING MODE
2nd stage (t1 ≤ t ≤ t2)

19. CONVERTER ANALYSIS TO OVERLAPPING MODE
3rd stage (t2 ≤ t ≤ t3)

20. CONVERTER ANALYSIS TO OVERLAPPING MODE
4th stage (t3 ≤ t ≤ T)

21. DUTY CYCLE VARIATION
where,

22. CONTROL STRATEGY
It’s based on OCC techinque for VIENNA with main features:
Constant switching frequency;
Simple and reliable;
No need for multipliers;
No three-phase input AC voltage sensors are required.

23. CONTROL STRATEGY
Schematic of three-PFC controller for VIENNA rectifier

24. CONTROL STRATEGY

25. DIGITAL IMPLEMENTATION
It’s implemented using the Cyclone® II EP2C20F484C7 FPGA and programmed with Quartus II®
The block schematic diagram in Quartus II®

26. SIGNAL CONDITIONING

27. VOLTAGE REGULATOR

28. SAW-TOOTH CARRIERS

29. PWM MODULATOR

30. DESIGN AND EXPERIMENTAL RESULTS
Design specifications
Output power
Po = 9kW
Mains input voltage
V1 = 110Vac
Output voltage
Vo= Vdc
Mains frequency
fr = 60Hz
Output voltage ripple
ΔVo = 5%.Vo
Input current ripple
ΔI1 = 20%.I1
Theoretical efficiency
η = 0,97
Inductors
L = 60μH
NEE – 65/33/26 (Thornton Ipec)
NL = 16 turns (37 x 22AWG)
Autotransformers
NEE – 55/28/21 (Thornton Ipec)
Np = Ns = 12 turns (15 x 22AWG)
Switches
IRGP50B60PD1
Diodes
30EPH06
Capacitors
C =1360μF (2x680µF/ 350V)

31. DESIGN AND EXPERIMENTAL RESULTS

32. DESIGN AND EXPERIMENTAL RESULTS
Input voltage and current
Simulation results
Preliminaries experimental results
100V/div, 20A/div, 5ms/div

33. DESIGN AND EXPERIMENTAL RESULTS
Output voltage
Simulation results
Preliminaries experimental results
100V/div, 2ms/div

34. DESIGN AND EXPERIMENTAL RESULTS
Control voltages in each phase
Control voltages in each phase
Simulation results

35. CONCLUSIONS Important features observed: High input power factor;
New simple control scheme using digital control with FPGA;
Reduced conduction losses;
Reduced volume and weight of magnetics comp.;
About 53% of volume if compared with VIENNA topology
Conection between input and output enabling by-pass without isolating transformer.

36. FUTURE WORKS Total output power experimental results;
Development of a complete UPS with inverter stage.

37. ACKNOWLEDGEMENT
Universidade Federal
do Ceará

38. APEC 2010
THE APPLIED POWER ELECTRONICS CONFERENCE AND EXPOSITION
February 21-25, 2010, Palm Springs, USA
Three-phase Voltage Doubler Rectifier Based on Three-Switching Cell For Uninterruptible Power Supply Applications Using FPGA
Raphael A. da Câmara -
Paulo P. Praça, Cícero M. T. Cruz, René P. Torrico-Bascopé,
Carlos E. A. Silva, Demercil D. S. Oliveira Jr., Luiz H. S. C. Barreto
Federal University of Ceará - Brazil 38