1. CSCI206 - Computer Organization & Programming
Improved Caches
zyBook: 12.4

2. Cache Write Policy Is the data in the cache? yes no
Update the cache and main memory (write through)
Update the cache only (write back) no
load data into cache and proceed as if it were a hit (write allocate)
update main memory without bringing the block into the cache (no write allocate)

3. Write Policy Write through - all writes go immediately to memory
pro: easy to manage
con: main memory is slow, therefore writes are slow
Write Back - write in the cache and only update memory when the block is removed from the cache
pro: fast writes
con: inconsistent memory (multicore), may increase read miss time (due writeback of an evicted block)

4. Write Back To implement, add a dirty bit to the cache
Index
Value
Valid
Tag
Dirty 1
To implement, add a dirty bit to the cache
When data is loaded to the cache it is set to 0
If any byte in the block is modified, set it to 1
When the block is removed from the cache, check the dirty bit
if 1 write the block to main memory

5. 3 Causes of cache misses

6. 3 Causes of cache misses Compulsory Capacity Conflict
The first time a block is accessed it will never be in the cache.
Capacity
The program is accessing more data than will fit in the cache (e.g., a 4 KB cache processing a 16 KB array).
Conflict
The program is using data stored at different memory locations but the same location in the cache.

7. Improving Cache Performance
Compulsory misses can be reduced by increasing the block size
This uses spatial locality to preload data near past memory references

8. Block size example let A be at address 0x7000 0000 int A[1024];
for (i = 0; i < 1024; i++)
A[i] = i;
16 Byte Block
A[0]
A[1]
A[2]
A[3]
Miss, hit, hit, hit, <repeat>
25% miss rate
let A be at address 0x
Memory accesses:
W 0x
W 0x
W 0x
W 0x C 4
W 0x
W 0x
32 Byte Block
A[0]
A[1]
A[2]
A[3]
A[4]
A[5]
A[6]
A[7]
Miss, hit, hit, hit, hit, hit, hit, hit, <repeat>
12.5% miss rate

9. Improving Cache Performance
Capacity misses are related to the number of indexes in the cache
Increasing cache size, increases the number of indexes, and reduces capacity misses
Decreasing block size also increases the number of cache indexes and can reduce capacity misses

10. Improving Cache Performance
Conflict misses can be reduced by changing the cache algorithm
A direct mapped cache has a many to one mapping of address to cache index
We want alternatives

11. Fully Associative Cache
Address
Value 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Fully Associative Cache
Locate blocks anywhere in the cache
cache does not have an index
eliminates conflict misses
To check for hit, compare every tag in the cache to the tag for the memory address
search the cache - O(N)
Value
Valid
Tag